Performance Analysis of CMOS Full adders using 180nm Technology
Citation
Sai Venkatramana Prasada G S, Dr.G Seshikala, Dr.Niranjana S, Rashmi P C "Performance Analysis of CMOS Full adders using 180nm Technology", International Journal of Engineering Trends and Technology (IJETT), V51(2),93-96 September 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
This paper presents the comparative
analysis of power, delay and power delay product
(PDP) of different Full adder circuit designs.
Addition is the fundamental building block for
processor architectures and for any VLSI
application specific designs. Here group of different
full adder structures are considered. Performance
parameters in terms of power and delay are
analyzed for special full adders like complementary
and level restoring carry logic (CLRCL), static
energy recovery full adder (SERF), GDI_XOR full
adder also. All adder designs are simulated in
Mentor Graphics tool with 180nm technology.
Among the simulated full adders 8Transistor full
adder is the high performed adder cell, which is the
option for an efficient VLSI design.
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Keywords
CLRCL, GDI_XOR, PDP, SERF.