DA Algorithm Based Reconfigurable 16-Tap FIR Filter Design Analysis
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2018 by IJETT Journal | ||
| Volume-60 Number-1 |
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| Year of Publication : 2018 | ||
| Authors : Agamreet Kaur, Rajesh Mehra |
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| DOI : 10.14445/22315381/IJETT-V60P210 |
Citation
Agamreet Kaur, Rajesh Mehra"DA Algorithm Based Reconfigurable 16-Tap FIR Filter Design Analysis", International Journal of Engineering Trends and Technology (IJETT), V60(1),71-75 June 2018. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
In this paper, 16-Tap FIRlow pass filter has been designed and implemented on FPGA target device. The filter has been designed and analyzed using different folding factors in order to optimize speed and area parameters.A multiplier less Distributed Arithmetic algorithm(DALUT) is used to provide optimized cost effective reconfigurable FIR filter. The proposed filter has been designed and simulated usingMATLAB. Its behavioral simulation and synthesis are performed using ISE simulator and Xilinx Synthesis tool on sparten-3E based on 3s500efg320-5 FPGA device. The synthesis results show area consumption from And maximum operating frequency from42.093 MHz to 60.680 MHzwith increase in folding factor from 2 to 8.
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Keywords
DALUT, Digital filter,FPGA, VLSI