Design of Cryptographic Encryption Processor
 |
International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2018 by IJETT Journal | ||
| Volume-63 Number-2 |
||
| Year of Publication : 2018 | ||
| Authors : Abhishek Kunte and Dhanabal R |
||
| DOI : 10.14445/22315381/IJETT-V63P216 |
Citation
MLA Style: Abhishek Kunte and Dhanabal R"Design of Cryptographic Encryption Processor" International Journal of Engineering Trends and Technology 63.2 (2018): 91-93.
APA Style:Abhishek Kunte and Dhanabal R (2018). Design of Cryptographic Encryption Processor. International Journal of Engineering Trends and Technology, 63(2), 91-93.
Abstract
Cryptography still serves to be a major way for communicating highly confidential information. Hence it is essential for a cryptographic processor to have high performance, low power, flexibility in hardware and most importantly highly encrypted data set which could not be hacked by any other unauthorized person. While there are various algorithms available for cryptography, all algorithms focus on encrypting the data in different ways such that the data remains private and can be accessed via highly confidential private key. In this work, the data is encrypted using modified AES algorithm by passing it through various stages of LUT’s and shift registers. The multiple stages of encryption ensure highly encrypted data set. The performance metrics of the processor is measured on various parameters like throughput, power consumed, etc. By using the modified AES algorithm for encryption, the processor achieves a throughput of 4Gbps for one program element block at 1GHz frequency.
Reference
[1] Amit Kumar, Manoj Kumar, and P. Balramudu“Implementation of AES algorithm using VHDL”, Proceedings of the IEEE 2017 International Conference on Computing Methodologies and Communication (ICCMC).
[2] Ukrit Arom-oon “An AES Cryptosystem For Small Scale Network”, Third Asian Conference on Defence Technology (3rd ACDT).
[3] Shoucheng Wang, Jinhui Xu, Yingjian Yan and Gongli Li, “A High-Efficiency Reconfigurable Cryptographic Processor”, 2016 IEEE International Conference on Integrated Circuits and Microsystems.
[4] Ross Anderson, Mike Bond, Jolyon Clulow andSergei Skorobogatov“Cryptpgraphic Processors – A Survey”.
[5] Amar Rasheed, M. Cotter, B. Smith, D. Levan, and S. Phoha “Dynamically Reconfigurable AES Cryptographic Core for Small, Power Limited Mobile Sensors”, 978-1-5090-5252-3/16/$31.00 ©2016 IEEE.
[6] Gokhan Sayilar and Derek Chiou “Cryptoraptor: High Throughput Reconfigurable Cryptographic Processor”, 978-1-4799-6278-5/14/$31.00 ©2014 IEEE.
Keywords
AES algorithm, Cryptography, LUT’s, Shift Registers, Throughput.