IJBTT

Impact of Channel Length Variation on Short Channel Effect Parameters of Two Different GAA Nanowire Transistor Structure

	International Journal of Engineering Trends and Technology (IJETT)
	© 2019 by IJETT Journal
	Volume-67 Issue-8
	Year of Publication : 2019
	Authors : Riaz Uddin Ahmed, Riya Saha,MdMohsinur Rahman Adnan, ShowmikSingha.
	DOI :  10.14445/22315381/IJETT-V67I8P214

Citation 

MLA Style: Riaz Uddin Ahmed, Riya Saha,MdMohsinur Rahman Adnan, ShowmikSingha "Impact of Channel Length Variation on Short Channel Effect Parameters of Two Different GAA Nanowire Transistor Structure" International Journal of Engineering Trends and Technology 67.8 (2019):83-86.

APA Style:Riaz Uddin Ahmed, Riya Saha,MdMohsinur Rahman Adnan, ShowmikSingha. Impact of Channel Length Variation on Short Channel Effect Parameters of Two Different GAA Nanowire Transistor Structure  International Journal of Engineering Trends and Technology, 67(8),83-86.

Abstract
Two different structures of junctionless nanowire transistor have been introduced in this work and their performance has been analyzed. Previously proposed two structures: rectangular GAA junctionless nanowire transistor, cylindrical GAA nanowire transistor are analyzed using the CVT model approach by TCAD Silvaco Atlas. Short channel effect parameters like Drain induced barrier lowering (DIBL), Threshold Voltage Roll off (TVRO), Subthreshold Swing (SS), on state and off state current ratio (I_on/I_off) for the mentioned structures of n-channel JLNW transistor are analyzed. Simulation has been executed by varying channel length (L_g) and oxide thickness (T_ox) to observe the electrical transport characteristics. In quintessence, JLRG is better in the threshold voltage roll off parameter over channel length alteration. Although JLCG is better candidate in other SCE parameters like Ion/Ioff ratio, SS and DIBL than JLRG.

Reference
[1] Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. DehdashtiAkhavan, P. Razavi, J. Colinge. Junctionless nanowire transistor (JNT): Properties and design guidelines. 2010 Proceedings of the European Solid State Device Research Conference, 2010.
[2] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’neill, A. Blake, M. White, et al., “Nanowire transistors without junctions,” Nature nanotechnology, vol. 5, no. 3, p. 225, 2010.
[3] M. M. Islam, S. Singha, M. M. R. Adnan,T.Dev, Design and Characterization of Two Different Structure of Junctionless Nanowire Transistor Considering Quantum Ballistic Transport Model,2018.
[4] V. Narula, C. Narula, & Singh, J. Singh, “Investigating short channel effects and performance parameters of double gate junctionless transistor at various technology nodes”. 2015 2nd International Conference on Recent Advances in Engineering & Computational Sciences (RAECS), 2015.
[5] E.H. Minhaj, S.R. Esha, M. M. R. Adnan, & T. Dey, Impact of Channel Length Reduction and Doping Variation on Multigate FinFETs. 2018 International Conference on Advancement in Electrical and Electronic Engineering (ICAEEE), 2018.
[6] T. Goudon, V. Miljanovic, & C. Schmeiser, “On the Shockley–Read–Hall Model: Generation-Recombination in Semiconductors”. SIAM Journal on Applied Mathematics, vol. 67, no. 3, p. 1183, 2017.
[7] Atlas User`s Manual: Device Simulation Software, 2008.
[8] B. Singh, D. Gola, K. Singh, E. Goel, S.Kumar, &S.jit, Analytical Modeling of Channel Potential and Threshold Voltage of Double-Gate Junctionless FETs With a Vertical Gaussian-Like Doping Profile. IEEE Transactions on Electron Devices, Vol.63, no.6, p. 2299, 2016.
[9] K. E. Kaharudin, F. Salehuddin, A. H. Hamidon, A. S. M. Zain, M. N. I. Abd Aziz and I. Ahmad, VARIABILITY ANALYSIS OF PROCESS PARAMETERS ON SUBTHRESHOLD SWING IN VERTICAL DG-MOSFET DEVICE. Journal of Engineering and applied sciences. Vol.11, no.5, p.3137, 20
16. [10] C.N. Saha, R. Fabiha, & M.S. Islam, Effect of dielectric constant and oxide thickness on the performance analysis of symmetric double gate stack-oxide junctionless field effect transistor in subthreshold region. 2017 International Conference on Electrical, Computer and Communication Engineering (ECCE), 2017.

Keywords
Cylindrical gate structure, rectangular gate structure, CVT, short channel effects, DIBL, Ion/Ioff Ratio, threshold voltage, Silvaco TCAD