Design And Modelling An Attack on Multiplexer Based Physical Unclonable Function

Design And Modelling An Attack on Multiplexer Based Physical Unclonable Function

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2020 by IJETT Journal
Volume-68 Issue-6
Year of Publication : 2020
Authors : Abhijith Manchikanti Venkata, Dinesh Reddy Jeeru, Vittal K.P.
DOI :  10.14445/22315381/IJETT-V68I6P210S

Citation 

MLA Style: Abhijith Manchikanti Venkata, Dinesh Reddy Jeeru, Vittal K.P.  "Design And Modelling An Attack on Multiplexer Based Physical Unclonable Function" International Journal of Engineering Trends and Technology 68.6(2020):63-67. 

APA Style:Abhijith Manchikanti Venkata, Dinesh Reddy Jeeru, Vittal K.P. . Design And Modelling An Attack on Multiplexer Based Physical Unclonable Function  International Journal of Engineering Trends and Technology, 68(6),63-67.

Abstract
This paper deals with study of the physical unclonable functions and specifically the design of arbiter based PUF (APUF) and extends the work on different types of attacks on the PUF designs to break the security of the device, which includes advanced computational algorithms. Machine learning (ML) based attacks are successful in attacking existing designs. So in this, the resistance of the modified, proposed design of APUF is examined by modelling the attack based on the logistic regression a MLbased algorithm. The design is validated on Basys-3 Artix -7 FPGA board with a part number (xc7a35tcpg236-1).

Reference

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Keywords
PUF, Machine Learning, Verilog, FPGA, Logistic Regression, Hardware Security.