A New Dual-Differential Full-Adder Design for CED-based Fault-Tolerant Circuits

A New DualDifferential FullAdder Design for CEDbased FaultTolerant Circuits
  IJETT-book-cover           
  
© 2021 by IJETT Journal
Volume-69 Issue-12
Year of Publication : 2021
Authors : Mouna Karmani, Noura Ben Hadjyoussef, Belgacem Hamdi, Mohsen Machhout
DOI :  10.14445/22315381/IJETT-V69I12P231

How to Cite?

Mouna Karmani, Noura Ben Hadjyoussef, Belgacem Hamdi, Mohsen Machhout, "A New DualDifferential FullAdder Design for CEDbased FaultTolerant Circuits," International Journal of Engineering Trends and Technology, vol. 69, no. 12, pp. 257-266, 2021. Crossref, https://doi.org/10.14445/22315381/IJETT-V69I12P231

Abstract
In this work, we present a new dual-differential full-adder bit-slice design that can be used for implementing circuits with Concurrent Error Detection (CED) capability. The proposed design is suitable to realize applications needing diagnostics and maintenance in the field. The proposed design used a mixed DPL/PTL logic style design, requires only 24 transistors, and provides dual-differential outputs. To prove the proposed design efficiency, the circuit is designed and simulated using the standard 32 nm technology node. The proposed scheme can be used to ameliorate the circuit fault detection, fault-masking, and then fault tolerance capability. By using the proposed full-adder bit-slice, we have implemented and simulated a 4-bit ripple carry adder design realized using a mixed CMOS/DPL/PTL logic style design. The simulation results prove the acceptable electrical behavior of the implemented 4-bit ripple carries adder design.

Keywords
full-adder; dual-differential; CED; 32nm technology node;

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