Analysis of Subthreshold Characteristics for Top and Bottom Flatband Voltages of Junction less Double Gate MOSFET

Analysis of Subthreshold Characteristics for Top and Bottom Flat-band Voltages of Junction less Double Gate MOSFET

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2021 by IJETT Journal
Volume-69 Issue-3
Year of Publication : 2021
Authors : Hakkee Jung
DOI :  10.14445/22315381/IJETT-V69I3P201

Citation 

MLA Style: Hakkee Jung  "Analysis of Subthreshold Characteristics for Top and Bottom Flat-band Voltages of Junction less Double Gate MOSFET" International Journal of Engineering Trends and Technology 69.3(2021):1-6. 

APA Style:Hakkee Jung. Analysis of Subthreshold Characteristics for Top and Bottom Flat-band Voltages of Junction less Double Gate MOSFET  International Journal of Engineering Trends and Technology, 69(3),1-6.

Abstract
The subthreshold characteristics are analyzed for the difference of the top and bottom flat-band voltage and dielectric constant of the junctionless double gate (JLDG) MOSFET. The potential distribution model of the asymmetric JLDG MOSFET is presented, and short-channel effects such as the degradation of subthreshold swing, the threshold voltage shift, drain induced barrier lowering (DIBL), and on-off current ratio are analyzed according to the flat-band voltage and the dielectric constant. As a result, the threshold voltage and on-off current ratio increase when the difference of the top and bottom flat-band voltage increases, but the subthreshold swing decreases. The DIBL is not affected by the flat-band voltage difference. As the constant dielectric increases, the threshold voltage and on-off current ratio increase, but DIBL and subthreshold swing decrease. In the case of the dielectric constant of 3.9, when the difference of the flat-band voltage increases from Vfbb-Vfbf=-0.5 V to Vfbb-Vfbf=0.5 V, the threshold voltage increases by 0.5 V, while the on-off current ratio increases by about 103. However, the increasing rate of the threshold voltage remains unchanged, and the on-off current ratio increases by about 106 when the dielectric constant is 25.

Reference
[1] R. U. Ahmed, R. Saha, M. R. Adnan, and ShowmikSingha, Impact of Channel Length Variation on Short Channel Effect Parameters of Two Different GAA Nanowire Transistor Structure, International Journal of Engineering Trends and Technology, 67(8) (2019) 83-86.
[2] V. Kumar, R. Gupta, R. P. P. Singh, and R. Vaid, Performance Analysis of Double Gate n-FinFET Using High-k Dielectric Materials, International Journal of Innovative Research in Science, Engineering and Technology, 5(7) (2016) 13242-13249.
[3] K. Liu, and L. Yang, Investigation on Fin and Gate Line Edge Roughness Effects for Sub-22 nm Inversion-Mode and Junctionless FinFETs, International Journal of Engineering Trends and Technology, 40(2) (2016) 72-76.
[4] L. Chen, M. Yeh, Y. Lin, K. Lin, M. Wu, V. Thirunavukkarasu and Y. Wu, The Physical analysis on the electrical junction of junctionless FET, AIP ADVANCES, 7(2) (2017) 025301.
[5] G. L. Priya and N. B. Balamurugan, New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation, International Journal of Electronics and Communications, 99 (2019) 130-138.
[6] Q. Xie, Z. Wang, and Y. Taur, Analysis of Short-Channel Effects in Junctionless DG MOSFETs, IEEE Trans. Electron Devices, 64(8) (2017) 3511-3514.
[7] Raksharam, and A. K. Dutta, A unified analytical drain current model for Double-Gate Junctionless Field-Effect Transistors including short channel effects, Solid-State Electronics, 130 (2017) 33-40.
[8] J. P. Colinge, A. Kranti, R. Yan, C. W. Lee, I. Ferain, R. Yu, N. D. Akhavan, and P. Razavi, Junctionless Nanowire Transistor (JNT): Properties and design guidelines, Solid-State Electronics, 65-66 (2011) 33-37.
[9] S. K. Yadav, and R. Singh, Analysis and Comprehensive study of Junction-less transistor, Intl. J. Eng. Sci. Adv. Research, 4(2) (2018) 103-120.
[10] J. Ajayan, D. Nirmal, P. Prajoon and J. C. Pravin, Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-k dielectric for high-speed applications, International Journal of Electronics and Communications, 79 (2017) 151-157.
[11] A. Balhara and D. Punia, Design and Analysis of Double Gate MOSFET Devices using High-k Dielectric, International Journal of Electrical Engineering, 7(1) (2014) 53-60.
[12] Nirmal, V. Kumar, P. C. Samuel, Shruthi, D. M. Thomas and M. Kumar, Analysis of Dual Gate MOSFETs Using High k Dielectrics, in Proc. 2011 3rd International Conference on Electronics Computer Technology, (2011) 22-25.
[13] P.S. Raja, R. J. Daniel, Effect of gate dielectric on the threshold voltage of nanoscale MOSFETs, International Journal of Engineering Research and Development, 5(3) (2012) 93-104.
[14] Sakshi, S. Dhariwal and A. Singh Analyzing the effect of gate dielectric on the leakage currents, MATEC Web of Conferences, 57 (2016) 01028.
[15] M. Karbalaei, D. Dideban, and H. Heidari, Impact of high-k gate dielectric with different angles of coverage on the electric characteristics of gate-all-around field-effect transistor: A simulation study, Results in Physics, 16 (2020) 102823. [16] Y. H. Shin, S. Weon, D. Hong and I. Yun, Analytical Model for Junctionless Double-Gate FET in Subthreshold Region, IEEE Trans. Electron Devices, 64(4) (2017) 1433-1440.
[17] H. Abebe, E. Cumberbatch, H. Morris, V. Tyree, T. Numata, and S. Uno, Symmetric and Asymmetric Double Gate MOSFET Modeling, J. of Semiconductor Technology and Science, 9(4) (2009) 225-232.
[18] Z. Ding, G. Hu, J. Gu, R. Liu, L. Wang, and T. Tang, An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs, Microelectronics J., 42(3) (2011) 515-519.
[19] H. Jung, Top and Bottom Gate Oxide Thickness Dependent Subthreshold Swing in Asymmetric Junctionless Double Gate MOSFET, International Journal of Electrical and Electronic Engineering & Telecommunications, 8(5) (2019) 292-296.
[20] H. Jung, Analysis of subthreshold swing in junctionless double-gate MOSFET using stacked high-k gate oxide, International Journal of Electrical and Computer Engineering, 11(1) (2021) 240-248.
[21] P. K. Tiwari, C. R. Panda, A. Agarwal, P. Sharma, and S. Jit, Analytical Modeling of Effective Conduction Path Effect(ECPE) on the Subthreshold Swing of DG-MOSFETs, in Proc. of the 2009 Spanish Conference on Electron Devices, (2009) 136-139.
[22] A. Ortiz-Conde, F. J. Carcia-Sanchez, J. Muci, A. T. Barrios, J. J. Liou, and C. Ho, Revisiting MOSFET threshold voltage extraction methods, Microelectronics Reliability, 53(1) (2013) 90-104.
[23] S. Dimitrijev, Principles of Semiconductor Devices, 2nd ed. New York, NY: Oxford University Press, (2012) 453.
[24] H. Jung, SPICE Model of Drain Induced Barrier Lowering in Symmetric Junctionless Double Gate MOSFET, International Journal of GEOMATE, 16(55) (2019) 20-27.
[25] T. Kang, C. Hsu, H. Liu, F. Chien, and C. Lin, Effect of transistor behavior on off-state current in poly-Si junctionless nanowire thin-film transistor, Jpn. J. Appl. Phys., 59 (2020) 126503.
[26] P. K. Asthana, Y. Goswami, S. Basak, S. B. Rahi, and B. Ghosh, Improved performance of a junctionless tunnel field-effect transistor with a-Si and SiGe heterostructure for ultra low power applications, RSC Advances, 5(60) (2015) 48779-48785.
[27] J. Innocenti, L. Welter, F. Julien, L. Lopez, J. Sonzogni, S. Niel, A. Regnier, E. Paire, K. Labory, E. Denis, J. Portal, and P. Masson, Dynamic Power Reduction through Process and Design Optimizations on CMOS 80 nm Embedded Non-Volatile Memories Technology, in Proc. 2014 IEEE 57th international Midwest Symposium on Circuits and Systems (MWSCAS), College Station, TX, USA, (2014) 897-900.

Keywords
Threshold voltage, Subthreshold swing, DIBL, On-off current, Flat-band voltage, Dielectric constant.