An Ultra Low Current Mismatch Charge Pump and Loop Filter in 0.18um CMOS Process for Low Spur PLL Applications

An Ultra Low Current Mismatch Charge Pump and Loop Filter in 0.18um CMOS Process for Low Spur PLL Applications
  IJETT-book-cover           
  
© 2021 by IJETT Journal
Volume-69 Issue-6
Year of Publication : 2021
Authors : Dr. Pradeep B. Mane, Ms. Shobha N. Pawar
DOI :  10.14445/22315381/IJETT-V69I6P203

How to Cite?

Dr. Pradeep B. Mane, Ms. Shobha N. Pawar, "An Ultra Low Current Mismatch Charge Pump and Loop Filter in 0.18um CMOS Process for Low Spur PLL Applications," International Journal of Engineering Trends and Technology, vol. 69, no. 6, pp. 14-24, 2021. Crossref, https://doi.org/10.14445/22315381/IJETT-V69I6P203

Abstract
Miniaturization is the need of advanced satellite, broadcasting and telecommunication networks. Phase locked loops (PLL) are used in satellite transceivers for carrier generation. It is of great significance to design PLL on single chip with less switching time, large bandwidth and specifically minimal phase noise/reference spur. Charge pump (CP) based PLL is low cost solution for frequency synthesis it also exhibits a wide capture range without offset but the downside is it generates high reference spur owing to current mismatch. This paper discusses non-ideal effects of the charge pump including current mismatch, charge injection and charge sharing and suggests mitigation techniques for them. Paper also compares conventional charge pump architectures and suggests best suitable architecture for integrated PLL. Paper later gives design and implementation of CP and loop filter(LF) using 0.18um CMOS process with 1.8V supply voltage. DC analysis of the CP circuit gives IUP and IDOWN current values of 469.9 ?A and 410.9 ?A respectively which gives negligible current mismatch ratio of 0.13%. LF is designed with loop bandwidth of 5MHz and achieves 0.8us settling time.

Keywords
Charge Pump (CP), Phase Locked Loops (PLL), Current Mismatch, Charge Sharing, Clock Feedthrough

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