FPGA based Matched Filter Design using Modified Masking Signal Generator

FPGA based Matched Filter Design using Modified Masking Signal Generator
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© 2022 by IJETT Journal
Volume-70 Issue-10
Year of Publication : 2022
Authors : Arunjyothi Eddla, Venkata Yasoda Jayasree Pappu
DOI : 10.14445/22315381/IJETT-V70I10P201

How to Cite?

Arunjyothi Eddla, Venkata Yasoda Jayasree Pappu, "FPGA based Matched Filter Design using Modified Masking Signal Generator," International Journal of Engineering Trends and Technology, vol. 70, no. 10, pp. 1-7, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I10P201

Abstract
Nowadays, digital filters are broadly used in various signal and image processing applications due to their efficacy in filtering processes. However, the implementation of digital filters is suffered from various issues, such as high area and power consumption. An effective filter must be implemented to minimise the area while minimizing power consumption to overcome this. In this paper, the Modified Masking Signal Generator (MMSG) is proposed for designing the Matched Filter (MF) over Field-Programmable Gate Array (FPGA). The proposed MMSG uses only a smaller number of resources during the filtering processes, which helps to decrease the overall hardware resources. The performance of the MF-MMSG architecture is analyzed using slices, slice registers; Slice Look Up Tables (SLUTs), logical elements, flip flops, bonded Input/Output Block (IOB), power, delay and operating frequency. The existing research, namely Two-Dimensional MF (TDMF) and Matched Filtering Unit (MFU) with Synthetic Aperture Radar (SAR), are used to evaluate the MF-MMSG architecture. The SLUTs of the MF-MMSG designed in Zynq Ultrascale+ FPGA is 4120, less than the MFU-SAR.

Keywords
Digital Filters, Field-Programmable Gate Array, Matched Filter, Modified Masking Signal Generator, Hardware Utilization, Power Consumption.

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