Retention Time Optimization In 3TDRAM Using Parametric Variation In Nanometer Regime

Retention Time Optimization In 3TDRAM Using Parametric Variation In Nanometer Regime
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© 2022 by IJETT Journal
Volume-70 Issue-2
Year of Publication : 2022
Authors : Amol S. Sankpal, D. J. Pete
DOI :  10.14445/22315381/IJETT-V70I2P220

How to Cite?

Amol S. Sankpal, D. J. Pete, "Retention Time Optimization In 3TDRAM Using Parametric Variation In Nanometer Regime," International Journal of Engineering Trends and Technology, vol. 70, no. 3, pp. 179-184, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I2P220

Abstract
Retention time play a very prominent role in dynamic random-access semiconductor memory. During the implementation of low power devices, VLSI designer faces the problem of leakage current, Small device geometry and minimum area utilization on a silicon wafer. Moore’s law states that no of transistor doubles on a small portion of a silicon wafer after every two years. On a nanometer scale, CMOS technology has certain limitations due to the abrupt effect of small device geometry and leakage current. In this paper, analysis of leakage current and leakage power is done and mainly focus on improvement of retention time in 3TDRAM using leakage reduction finfet technology is proposed. Leakage reduction finfet technology is a leakage reduction schematic design in 3TDRAM that overcomes the issues related to traditional CMOS technology, and it does not require additional circuitry. Cmos and double gate finfet technology are proposed for implementation of 3TDRAM using cadence tool at 90nm technology. 3TDRAM is examined with Variation in supply voltage and capacitance value for CMOS and double gate finfet technology. As the results are compared, Retention time is more improved in double gate finfet technology as compared to CMOS technology is observed.

Keywords
Retention Time, Refresh frequency, Leakage Current, Leakage Power, Average Current, Average Power.

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