Ku Band Ultra-Low Phase Noise PLL Frequency Synthesizer using 0.18 μm CMOS Process
Ku Band Ultra-Low Phase Noise PLL Frequency Synthesizer using 0.18 μm CMOS Process
|© 2022 by IJETT Journal|
|Year of Publication : 2022|
|Authors : Shobha N. Pawar, Pradeep B. Mane, Milind P. Gajare
|DOI : 10.14445/22315381/IJETT-V70I8P202|
How to Cite?
Shobha N. Pawar, Pradeep B. Mane, Milind P. Gajare, "Ku Band Ultra-Low Phase Noise PLL Frequency Synthesizer using 0.18 μm CMOS Process," International Journal of Engineering Trends and Technology, vol. 70, no. 8, pp. 10-25, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I8P202
In this era of technology scaling, it is of prime importance to design a frequency synthesizer on a single chip to be used as a frequency multiplying transceiver. Presently, work is unavailable for the entire Ku (12 to 18GHz) band. Single-chip, wideband synthesizers are not available. Whereas in available wideband high-frequency PLL chips, entire elements are not integrated on a single chip, VCO or loop filters are externally connected. This paper presents a 12-18 GHz charge pump-based type-2, integer-N Phase Locked Loop-based frequency synthesizer designed on a single chip using0.18 μm CMOS technology. This PLL is intended to be used as the local oscillator (LO) in potential satellite communication applications. The rigorous phase noise analysis of the PLL in terms of out-of-band and in-band phase noise is performed. This suggests the requirement of block-wise performance improvement for extenuating the practical limits imposed during CMOS layout. Measurement results show that the size of the fabricated chip is only 0.076mm2, which can scale down to 50% by connecting Voltage Controlled Oscillator (VCO) outside the chip. Outstanding phase noise of -122.83dBc/Hz is measured at 1MHz offset when running at14.28GHz oscillation frequency. Process Voltage Temperature (PVT) corner analysis gives a worst-case phase noise of - 120.59dBc/Hz and best case phase noise of-124.19dBc/Hz@1MHz offset, which makes implemented chip suitable for satellite communication applications. The dead zone of the Phase Frequency Detector (PFD) is reduced to 1psalong with the negligible charge pump current mismatch ratio of 0.13%. The circuit achieves a fabulous dynamic range of 0.3V to 0.9 V.
Phase Locked Loops (PLL), Type-2 PLL, Phase Noise, Ku-band, Voltage Controlled Oscillator (VCO).
 Albittar I.F and Dogan H, “A Novel Technique for Duty Cycle Correction for Reference Clocks in Frequency Synthesizers,” Elsevier Microelectronics Journal, vol. 67, pp. 176–182, 2017. http://dx.doi.org/10.1016/j.mejo.2017.07.002.
 Choi Y.C, Seong Y.J, Yoo Y.J, Lee S.K, Lopez M.V, Yoo H.J, “Multi-Standard Hybrid PLL with Low Phase-Noise Characteristics for GSM/EDGE and LTE Applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 10, pp. 3254-3264, 2015. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7225192.
 Eric Wagner and Gabriel M. Rebeiz, “A Very Low Phase-Noise Transformer-Coupled Oscillator and PLL for 5G Communications in 0.12 μmSiGeBiCMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 68, no. 4, 2020. DOI: 10.1109/TMTT.2019.2957372.
 G. Giustolisi, G. Palmisano, G. Palumbo, T. Segreto, “1.2-V CMOS Op-Amp with a Dynamically Biased Output Stage,” IEEE Journal of Solid-State Circuits, vol. 35, no. 4, pp. 632-636, 2000. https://ieeexplore.ieee.org/document/839923.
 Gao M.C, Bao K.Y, Huang F.Y, “A Broadband Low Phase Noise CMOS Voltage Controlled Oscillator for Ku Band,” IEEE International Conference on Integrated Circuits and Microsystems, 2016. https://ieeexplore.ieee.org/document/7813575.
 In IEEE, J. Prinzie et al., "A Fast Locking 5.8–7.2-GHz Fractional-N Synthesizer with Sub-2-us Settling in 22-nm FDSOI," Solid-State Circuits Letters, vol. 3, pp. 546-549, 2020. Doi: 10.1109/LSSC.2020.3036122.
 Gonzalez-Diaz V.R, Sanchez-Gaspariano L.A, Muniz-Montero C, Alvarado-Pulido J.J, “Improving Linearity in MOS Varactor-based VCOs through the Output Quiescent Bias Point,” INTEGRATION the VLSI Journal, vol. 55, pp. 274-280, 2016. http://dx.doi.org/10.1016/j.vlsi.2016.08.003.
 A. Sharkia, S. Aniruddhan, S. Mirabbasi and S. Shekhar, "A Compact, Voltage-Mode Type-I PLL with Gain-Boosted Saturated PFD and Synchronous Peak Tracking Loop Filter," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 43-53, 2019. Doi: 10.1109/TCSI.2018.2858197
 Lei Zhang, Zongmin Wang, Tieliang Zhang, et al., “An Improved Fast Acquisition Phase Frequency Detector for High-Speed PhaseLocked Loops”, AIP Conference Proceedings, vol. 18, 2018.
 Chen Yingmei et al., “Low-Jitter PLL based on Symmetric Phase-Frequency Detector Technique”, Analog IntegrCirc Sig Process, 2010.
 Pawar S.N and Mane P.B, “Wideband PLL Frequency Synthesizer: A Survey,” International Conference on Advances in Computing, Communication and Control (ICAC3), 2017. https://ieeexplore.ieee.org/document/8318773.
 Scotti G, Bellizia D, Trifiletti A, Palumbo G, “Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies,” IEEE Transactions On Large-Scale Integration (VLSI) Systems, vol. 25, no. 12, pp. 1-12, 2017. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8048001.
 Sung Sik Park et al., “Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications”, International Journal of Electrical and Computer Engineering (IJECE), vol. 8, no. 6, 2018.
 Y. Peng and L. Lu, "A 16-GHz Triple-Modulus Phase-Switching Prescaler and its Application to a 15-GHz Frequency Synthesizer in 0.18-$\mu$m CMOS," in IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 1, pp. 44-51, 2007. Doi: 10.1109/TMTT.2006.886908.
 Zhang Y, Tang X, Wei Z, Bao K, Jiang N, “A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Band Width Control,” Electronics, vol. 10, pp. 109, 2021. http://doi.org/10.3390/electronics10020109
 Mane P B and Pawar S N, “An Ultra-Low Current Mismatch Charge Pumpand Loop Filter in 0.18um CMOS Process for Low Spur PLL Applications”, International Journal of Engineering Trends and Technology, vol. 69, no. 6, pp. 14-24, 2021.
 Zhu W, Yang H, Gao T, Liu F, Yin T, Zang D, Zang H, “A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler,” IEEE Transactions on Large-Scale Integration (VLSI) Systems, vol. 23, no. 1, pp. 194-197, 2015. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6734682.
 Vaishali and R. K. Sharma, “An Improved Dynamic Range ChargePump with Reduced Current Mismatch for PLL Applications,” Second International Conference on Intelligent Computing and Control Systems, Madurai, India, 2018. Doi: 10.1109/ICCONS.2018.8663212.
 S. Jandhyala and S. Tapse, "A 1.3V–1.8V Configurable Phase-Locked Loop with an Adaptive Charge Pump," IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), pp. 138-140, 2016. Doi: 10.1109/DISCOVER.2016.7806236.
 A. G. Amer, S. A. Ibrahim and H. F. Ragai, "A Novel Current Steering Charge Pump with Low Current Mismatch and Variation," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1666-1669, 2016. Doi: 10.1109/ISCAS.2016.7538887.
 Chih-Ming Hung and K. K. O, "A Fully Integrated 1.5-V 5.5-Ghz CMOS Phase-Locked Loop," in IEEE Journal of Solid-State Circuits, vol. 37, no. 4, pp. 521-525, 2002. Doi: 10.1109/4.991390.
 R. A. Baki and M. N. El-Gamal, “A New CMOS Charge Pumpfor Low-Voltage (1V) High-Speed PLL Applications, Circuits and Systems,” ISCAS '03, Proceedings of the 2003 International Symposium, vol. 1, pp. I-657-I-660, 2003.
 J. Gupta, A. Sangal and H. Verma, "High-Speed CMOS Charge Pump Circuit for PLL Applications using 90nm CMOS Technology," World Congress on Information and Communication Technologies, pp. 346-349, 2011. Doi: 10.1109/WICT.2011.6141270.
 Zou Q, Ma K, Yeo K.S, Lim W.M, “Design of a Ku-Band Low-Phase-Noise VCO using the Dual LC Tanks,” IEEE Transactions on Circuits and Systems—Ii: Express Briefs, vol. 59, no. 5, pp. 262-266, 2012. https://ieeexplore.ieee.org/document/6189056
 Z. Zhang, H. Djahanshahi, C. Gu, M. Patel and L. Chen, "Single-Event Effects Characterization of LC-VCO PLLs in a 28-nm CMOS Technology", in IEEE Transactions on Nuclear Science, vol. 67, no. 9, pp. 2042-2050, 2020. Doi: 10.1109/TNS.2020.3008142.
 S. Ji, Y. Zhao, W. Xu, N. Yan and H. Min, "A Novel Charge Pump with Ultra-Low Current Mismatch and Variation for PLL," IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, pp. 1-4, 2020. Doi: 10.1109/ISCAS45731.2020.9180830.
 M. Leoncini, A. Bonfanti, S. Levantino and A. L. Lacaita, "Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 6, pp. 1968-1980, 2018. Doi: 10.1109/TCSI.2017.2767280.
 C. Ko, T. Kuan, R. Shen and C. Chang, "A 7-nm FinFET CMOS PLL With 388-fs Jitter and −80-dBc Reference Spur Featuring a Trackand-Hold Charge Pump and Automatic Loop Gain Control," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1043-1050, 2020. Doi: 10.1109/JSSC.2019.2959735.
 A. Homayoun and B. Razavi, "On the Stability of Charge-Pump Phase-Locked Loops," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 6, pp. 741-750, 2016. Doi: 10.1109/TCSI.2016.2537823.
 C. C. Boon, M. V. Krishna, M. A. Do, K. S. Yeo, A. V. Do and T. S. Wong, "A 1.2 V 2.4 GHz Low Spur CMOS PLL Synthesizer with a Gain Boosted Charge Pump for a Batteryless Transceiver," IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Singapore, pp. 222-224, 2012. Doi: 10.1109/RFIT.2012.6401667.
 D. Liao, Y. Zhang, F. F. Dai, Z. Chen and Y. Wang, "An mm-Wave Synthesizer with Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO," in IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 536-546, 2020. Doi: 10.1109/JSSC.2019.2959513.
 T. Wu, P. K. Hanumolu, K. Mayaram and U. Moon, "Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers," in IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 427-435, 2009. Doi: 10.1109/JSSC.2008.2010792.
 S. N. Pawar and P. B. Mane, "Design and Implementation of KU Band LC-VCO using 90nm CMOS Process," International Conference on Smart Electronics and Communication (ICOSEC), Trichy, India, pp. 1234-1238, 2020. Doi: 10.1109/ICOSEC49089.2020.9215283.
 X. Liu and H. C. Luong, "A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer with Frequency-Tracking Loop in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1051-1063, 2020. Doi: 10.1109/JSSC.2019.2954232.