Ku Band Ultra-Low Phase Noise PLL Frequency Synthesizer using 0.18 μm CMOS Process

Ku Band Ultra-Low Phase Noise PLL Frequency Synthesizer using 0.18 μm CMOS Process

© 2022 by IJETT Journal
Volume-70 Issue-8
Year of Publication : 2022
Authors : Shobha N. Pawar, Pradeep B. Mane, Milind P. Gajare
DOI : 10.14445/22315381/IJETT-V70I8P202

How to Cite?

Shobha N. Pawar, Pradeep B. Mane, Milind P. Gajare, "Ku Band Ultra-Low Phase Noise PLL Frequency Synthesizer using 0.18 μm CMOS Process," International Journal of Engineering Trends and Technology, vol. 70, no. 8, pp. 10-25, 2022. Crossref, https://doi.org/10.14445/22315381/IJETT-V70I8P202

In this era of technology scaling, it is of prime importance to design a frequency synthesizer on a single chip to be used as a frequency multiplying transceiver. Presently, work is unavailable for the entire Ku (12 to 18GHz) band. Single-chip, wideband synthesizers are not available. Whereas in available wideband high-frequency PLL chips, entire elements are not integrated on a single chip, VCO or loop filters are externally connected. This paper presents a 12-18 GHz charge pump-based type-2, integer-N Phase Locked Loop-based frequency synthesizer designed on a single chip using0.18 μm CMOS technology. This PLL is intended to be used as the local oscillator (LO) in potential satellite communication applications. The rigorous phase noise analysis of the PLL in terms of out-of-band and in-band phase noise is performed. This suggests the requirement of block-wise performance improvement for extenuating the practical limits imposed during CMOS layout. Measurement results show that the size of the fabricated chip is only 0.076mm2, which can scale down to 50% by connecting Voltage Controlled Oscillator (VCO) outside the chip. Outstanding phase noise of -122.83dBc/Hz is measured at 1MHz offset when running at14.28GHz oscillation frequency. Process Voltage Temperature (PVT) corner analysis gives a worst-case phase noise of - 120.59dBc/Hz and best case phase noise of-124.19dBc/Hz@1MHz offset, which makes implemented chip suitable for satellite communication applications. The dead zone of the Phase Frequency Detector (PFD) is reduced to 1psalong with the negligible charge pump current mismatch ratio of 0.13%. The circuit achieves a fabulous dynamic range of 0.3V to 0.9 V.

Phase Locked Loops (PLL), Type-2 PLL, Phase Noise, Ku-band, Voltage Controlled Oscillator (VCO).

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