IJBTT

Efficient Design of Rounding and Leading One-bit based Approximate Multipliers using Modified Static Segment Method for Error-Tolerance Applications

Efficient Design of Rounding and Leading One-bit based Approximate Multipliers using Modified Static Segment Method for Error-Tolerance Applications
	© 2023 by IJETT Journal
	Volume-71 Issue-1
	Year of Publication : 2023
	Author : D. Tilak Raju, Y. Srinivasa Rao
	DOI : 10.14445/22315381/IJETT-V71I1P218

How to Cite?

D. Tilak Raju, Y. Srinivasa Rao, "Efficient Design of Rounding and Leading One-bit based Approximate Multipliers using Modified Static Segment Method for Error-Tolerance Applications," International Journal of Engineering Trends and Technology, vol. 71, no. 1, pp. 201-212, 2023. Crossref, https://doi.org/10.14445/22315381/IJETT-V71I1P218

Abstract
Multiplication is one of the premier modules in Error-Tolerance applications. In the current scenario, approximate computing is employed for the subsisted exact multipliers to maintain the trade-off between area, delay and the efficiency of the multiplier. In the literature, few methods are explored for multiplier designs to tail off the ingested energy and amplify the digital circuit’s accuracy. But these designs failed to achieve efficient outcomes with accuracy when used for various applications. Hence, in this paper, in order to maintain the trade-off between design and Error Metrics (EM), leading-one bit and Rounding-based Static Segment Approximate Multipliers (LSSAM, RSSAM) are proposed along with the Modified Estimator Circuit (MEC). These designs bring about approximate multiplication using the leading unit, rounding, and barrel shifter. Furthermore, MEC is utilized to cut out the lower-order data of the input operand bit-width taken. Later, these multipliers are synthesized and simulated using software like Vivado, MATLAB, and Cadence RTL compiler, for the input bit-width extending from 8-bit to 32-bit. The obtained simulation results show that the chosen designs reduce the Design Metrics (DM) like power, delay, area, and energy on an average of 68.2 %, 35.4 %, 60.1 %, and 68.5 %, respectively, and boost up the EM like MRED, NED, WCE, and MED by 49.8%, 18.8%, 36.7%, and 47.2%, respectively, compared to that of prior designs. Moreover, by including the proposed designs in the Error-Tolerance applications, the PSNR (Peak Signal to Noise Ratio) and SSIM (Structural Similarity Index Metric) are greatly alleviated.

Keywords
Leading-One-Bit approach, Rounding approach, Static segment method, Modified estimator circuit, Approximate computing.

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