A Comparative Study on 2D and 3D Floorplan Representations in VLSI Physical Design

A Comparative Study on 2D and 3D Floorplan Representations in VLSI Physical Design
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© 2024 by IJETT Journal
Volume-72 Issue-9
Year of Publication : 2024
Author : Sony Snigdha Sahoo, Prafulla Kumar Behera
DOI : 10.14445/22315381/IJETT-V72I9P108

How to Cite?
Sony Snigdha Sahoo, Prafulla Kumar Behera, "A Comparative Study on 2D and 3D Floorplan Representations in VLSI Physical Design," International Journal of Engineering Trends and Technology, vol. 72, no. 9, pp. 96-103, 2024. Crossref, https://doi.org/10.14445/22315381/IJETT-V72I9P108

Abstract
An important step in designing a chip layout is floorplanning. The location, shape, and size of modules in a chip are represented in the form of a floorplan. A floorplan shows the relative locations of electronic modules on a chip by dividing its core into rectangles.The quality of the chip implementation mostly depends on the floorplan's goodness. Effective placement of the modules and timing and congestion-related issuesare alsodependent on how well organized the floorplan is. Floorplan representation is the output of the floorplan phase and serves as an intermediary between floorplanning and other subsequent phases. Thus, choosing an appropriate floorplan representation is critical for any further implementation. This survey paper discusses and compares the features of various 2D floorplan representationssuch as mosaic floorplan, bounded slice line grid, corner block list, sequence pair, O-tree, binary slicing tree, B* tree,and their respective 3D counterparts.

Keywords
2D and 3D floorplan, B* Tree, Bounded slice line grid, Corner block list, Floorplan representation, O-tree, VLSI design.

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