Citation :

Rommel G. Gadia, Ramon G. Garcia, Marloun P. Sejera, "Adiabatic Techniques in VLSI Design (1992-2024): A 32-Year Bibliometric Review of Trends, Insights, and Future Directions," International Journal of Engineering Trends and Technology (IJETT), vol. 74, no. 4, pp. 116-131, 2026. Crossref, https://doi.org/10.14445/22315381/IJETT-V74I4P109

Abstract

The rapid requirement for low-power electronics has increased the interest in adiabatic logic circuits to minimize the energy dissipation in VLSI and low-power computing. Although the literature on different adiabatic logic families and their optimizations continues to grow, to the best of the authors' knowledge, an extensive bibliometric study of this topic remains scarce. This paper aims to provide a systematic analysis of the development of adiabatic logic over the last three decades by exploring underlying research themes, key contributors, and emerging gaps. Bibliometric analysis using Scopus and Web of Science (1992–2024), citation analysis, keyword co-occurrence mapping, and authorship network visualization with the Bibliometrix R package were performed. The findings show a growing number of publications, with an exponential growth in studies after 2000. Although the field's scientific productivity is high, international collaboration still seems limited. The review emphasizes the dominant research themes of energy-recovery approaches and low-power circuit optimization, and identifies what is currently lacking in the integration of adiabatic logic with future computing schemes. This work demonstrates an important concept and methodology for researchers about the importance of interdisciplinary studies and global collaboration in developing energy-efficient semiconductor technologies.

Keywords

Adiabatic Logic, Bibliometric Analysis, Energy-Efficient Circuits, Low-Power Electronics, VLSI.

References

[1] Suman Lata Tripathi, Parvej Ahmad Alvi, and Umashankar Subramaniam, Electrical and Electronic Devices, Circuits, and Materials: Technological Challenges and Solutions, John Wiley & Sons, 2021.
[CrossRef] [Google Scholar] [Publisher Link]

[2] William C. Athas et al., “Low-Power Digital Systems based on Adiabatic-Switching Principles,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 4, pp. 398-407, 1994.
[CrossRef] [Google Scholar] [Publisher Link]

[3] Noel B. Linsangan et al., “Implementation of a 4-bit Ripple Carry Full Adder of Mirror Design Style using Synopsys Generic 90nm Technology on a Full-Custom and Semi-Custom Design,” Journal of Telecommunication, Electronic and Computer Engineering (JTEC), vol. 10, no. 1-14, pp. 31-34, 2018
[Google Scholar] [Publisher Link]

[4] Antonio Blotti, and Roberto Saletti, “Ultralow-Power Adiabatic Circuit Semi-Custom Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 11, pp. 1248-1253, 2004
[CrossRef] [Google Scholar] [Publisher Link]

[5] A. Gangadhar, “Adiabatic Logic Technique with Lower Power for Logic Circuits,” 2022 International Conference on Electronics and Renewable Systems (ICEARS), Tuticorin, India, pp. 181-185, 2022.
[CrossRef] [Google Scholar] [Publisher Link]

[6] Minakshi Sanadhya, and Devendra Kumar Sharma, “Low Power Architecture of Logic Gates using Adiabatic Techniques,” Indonesian Journal of Electrical Engineering and Computer Science, vol. 25, no. 2, pp. 805-813, 2022.
[CrossRef] [Google Scholar] [Publisher Link]

[7] M. Vignesh, B. Paulchamy, and J. Jaya, “Designing of Adiabatic Approach for Power Efficient Full Adder Circuits,” 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC), Coimbatore, India, pp. 2032-2041, 2021.
[CrossRef] [Google Scholar] [Publisher Link]

[8] Senthil Kumaran Varadharajan, and Viswanathan Nallasamy, “Low Power VLSI Circuits Design Strategies and Methodologies: A Literature Review,” 2017 Conference on Emerging Devices and Smart Systems (ICEDSS), Mallasamudram, India, pp. 245-251, 2017.
[CrossRef] [Google Scholar] [Publisher Link]

[9] Paramjeet Chauhan, and Saptarshi Gupta, “Challenges and Future Perspectives of Low-Power VLSI Circuits: A Study,” Modern Electronics Devices and Communication Systems, pp. 561-569, 2023.
[CrossRef] [Google Scholar] [Publisher Link]

[10] Arnold C. Paglinawan et al., “Full Custom Rail-to-Rail Self-Calibrating Comparator for Low Voltage Successive Approximation Register Analog-to-Digital Converter,” Journal of Telecommunication, Electronic and Computer Engineering (JTEC), vol. 10, no. 1-14, pp. 41-45, 2018
[Google Scholar] [Publisher Link]

[11] Calvin Benzien C. Chan, Febus Reidj G. Cruz, and Wen-Yaw Chung, “A Single Ended Zero Aware Asymmetric 4T SRAM Cell,” 2017 IEEE 9^th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM), Manila, Philippines, pp. 1-4, 2017.
[CrossRef] [Google Scholar] [Publisher Link]

[12] Preethi, R. Sapna, and Mohammed Mujeer Ulla, Low-Power Methodologies and Strategies in VLSI Circuits, Energy Systems Design for Low-Power Computing, pp. 1-16, 2023.
[CrossRef] [Google Scholar] [Publisher Link]

[13] Anantha P. Chandrakasan, and Robert W. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits,” Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, 1995.
[CrossRef] [Google Scholar] [Publisher Link]

[14] Wu Yang, Amit Degada, and Himanshu Thapliyal, “Adiabatic Logic-based STT-MRAM Design for IoT,” 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Nicosia, Cyprus, 2022.
[CrossRef] [Google Scholar] [Publisher Link]

[15] Krithika Dhananjay, and Emre Salman, “SEAL-RF: Secure Adiabatic Logic for Wirelessly Powered IoT Devices,” IEEE Internet of Things Journal, vol. 10, no. 2, pp. 1112-1123, 2023.
[CrossRef] [Google Scholar] [Publisher Link]

[16] Wu Yang, Milad Tanavardi Nasab, and Himanshu Thapliyal, “Energy Efficient CLB Design based on Adiabatic Logic for IoT Applications,” Electronics, vol. 13, no. 7, pp. 1-16, 2024.
[CrossRef] [Google Scholar] [Publisher Link]

[17] Sravanthi Parepalli, Ramesh Kumar Aytha, and Sagar Reddy Vumanthala, “Energy Efficient Adiabatic Logic against Power Analysis Attacks for IOT Applications,” 2021 Fourth International Conference on Microelectronics, Signals & Systems (ICMSS), Kollam, India, pp. 1-4, 2021.
[CrossRef] [Google Scholar] [Publisher Link]

[18] Cole Terrell, and Himanshu Thapliyal, “Approximate Adder Circuits using Clocked CMOS Adiabatic Logic (CCAL) for IoT Applications,” 2020 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, 2020.
[CrossRef] [Google Scholar] [Publisher Link]

[19] Minakshi Sanadhya, and Devendra Kumar Sharma, “Adiabatic Logic based Shift Registers for Low Energy IoT Architecture-Design and Contemplation,” IET Communications, vol. 19, no. 1, pp. 1-9, 2022
[CrossRef] [Google Scholar] [Publisher Link]

[20] T.J. Nagalakshmi, “An Overview of Low Power Technologies and the Alternative Approaches for Low Power IOT Architecture,” 2024 Fourth International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT), Bhilai, India, pp. 1-6, 2024.
[CrossRef] [Google Scholar] [Publisher Link]

[21] S. Dinesh Kumar, and Himanshu Thapliyal, “Design of Adiabatic Logic-based Energy-Efficient and Reliable PUF for IoT Devices,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 16, no. 3, pp. 1-18, 2020.
[CrossRef] [Google Scholar] [Publisher Link]

[22] B.P. Bhuvana, and V.S. Kanchana Bhaaskaran, “Design and Analysis of IPAL for Ultra-Low Power CRC Architecture for Applications in IoT based Systems,” AEU - International Journal of Electronics and Communications, vol. 108, pp. 127-140, 2019.
[CrossRef] [Google Scholar] [Publisher Link]

[23] Srilakshmi Kaza, Venkata N Tilak Alapati, and Srinivasa Rao Kunupalli, “Energy Efficient Adder for Bio-Medical Applications,” 2018 IEEE Region 10 Humanitarian Technology Conference (R10-HTC), Malambe, Sri Lanka, pp. 1-5, 2018.
[CrossRef] [Google Scholar] [Publisher Link]

[24] J. Jebastine, and V. Nanammal, “Reversible - SAL Based Energy Efficient Design of CLA for DSP Application,” 2023 Eighth International Conference on Science Technology Engineering and Mathematics (ICONSTEM), Chennai, India, pp. 1-8, 2023.
[CrossRef] [Google Scholar] [Publisher Link]

[25] Ajay Prakash, Kush Thakur, and Ashwani K. Rana, “Performance Analysis of 4:1 Multiplexer using Adiabatic Logic for Low Power VLSI Application,” 2024 5^th International Conference for Emerging Technology (INCET), Belgaum, India, pp. 1-5, 2024.
[CrossRef] [Google Scholar] [Publisher Link]

[26] L. Dileshwar Rao et al., “FinFET based Adiabatic Logic Design for Low Power Applications,” 2017 International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS), Vellore, India, pp. 1-6, 2017.
[CrossRef] [Google Scholar] [Publisher Link]

[27] Mohammad Redwan Islam et al., “Modified ECRL Adiabatic Logic for Ultra Low Power VLSI Applications,” 2021 5^th International Conference on Electrical Engineering and Information Communication Technology (ICEEICT), Dhaka, Bangladesh, pp. 1-5, 2021.
[CrossRef] [Google Scholar] [Publisher Link]

[28] Minakshi Sanadhya, and Devendra Kumar Sharma, “D Flip-Flop Design by Adiabatic Technique for Low Power Applications,” Indonesian Journal of Electrical Engineering and Computer Science, vol. 29, no. 1, pp. 141-146, 2023.
[CrossRef] [Google Scholar] [Publisher Link]

[29] Nikita Mohanta, Prashant Yadav, and Jyoti Rani, “Design of Energy Efficient Logic Gates using CNTFET,” AIP Conference Proceedings, vol. 2352, no. 1, 2021.
[CrossRef] [Google Scholar] [Publisher Link]

[30] Josef-Stefan Wenzler et al., “A Nanomechanical Fredkin Gate,” Nano Letters, vol. 14, no. 1, pp. 89-93, 2014.
[CrossRef] [Google Scholar] [Publisher Link]

[31] Dilip P. Vasudevan et al., “Reversible-Logic Design with Online Testability,” IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 2, pp. 406-414, 2006.
[CrossRef] [Google Scholar] [Publisher Link]

[32] P. Kalyani, P. Satish Kumar, and Paidimarry Chandra Sekhar, “Energy Efficient Logic Gates using Subthreshold Adiabatic Logic,” 2016 International Conference on Inventive Computation Technologies (ICICT), Coimbatore, India, vol. 3, pp. 1-6, 2016.
[CrossRef] [Google Scholar] [Publisher Link]

[33] S. Kiran, and D.P, Raju, “Realization of Energy Efficient Logic Circuits using Adiabatic Technique,” International Journal of Computer Science information and Engineering Technologies, vol. 3, no. 4, pp. 1-13, 2015.
[Google Scholar]

[34] Rosemarie V. Pellegrino et al., “LOMI: Logic Gate Multiplexer Integrated Circuit using Verilog HDL,” 2021 5^th International Conference on Communication and Information Systems ICCIS, Chongqing, China, pp. 103-107, 2021.
[CrossRef] [Google Scholar] [Publisher Link]

[35] Minal Keote, and P.T. Karule, “Design and Implementation of Energy Efficient Adiabatic ECRL and Basic Gates,” 2015 International Conference on Soft Computing Techniques and Implementations (ICSCTI), Faridabad, India, pp. 87-91, 2015.
[CrossRef] [Google Scholar] [Publisher Link]

[36] Xuan Zhang et al., “An 8-bit Low Power Energy Recovery Full Adder Design,” 2017.
[Google Scholar]

[37] Ayodeji Olanite, Samuel Ouedraogo, and Murat Isik, “Comparative Analysis of Adiabatic Logic Circuits: Power Dissipation and Performance in FPGA and ASIC Implementations of ECRL and PFAL,” 2023 International Conference on Circuit Power and Computing Technologies (ICCPCT), Kollam, India, pp. 1303-1308, 2023.
[CrossRef] [Google Scholar] [Publisher Link]

[38] Sanjeev Kumar, “Implementation of Low Power CMOS Design using Adiabatic Improved Efficient Charge Recovery Logic,” International Journal of Scientific Engineering and Technology, vol. 3, no. 2, pp. 150-153, 2014. 
[Google Scholar] [Publisher Link]

[39] S. Maheshwari, “Adiabatic Approach for Low-Power Passive Near Field Communication Systems,” PhD Thesis, University of Westminster Computer Science and Engineering, 2018.
[CrossRef] [Google Scholar] [Publisher Link]

[40] Philip Teichmann et al., “Design of Ultra-Low-Power Arithmetic Structures in Adiabatic Logic,” 2007 International Symposium on Integrated Circuits, Singapore, pp. 365-368, 2007.
[CrossRef] [Google Scholar] [Publisher Link]

[41] Himanshi Sharma, and Rajan Singh, “Comparative Power Analysis of CMOS & Adiabatic Logic Gates,” 2015 International Conference on Green Computing and Internet of Things (ICGCIoT), Greater Noida, Delhi, pp. 7-11, 2015.
[CrossRef] [Google Scholar] [Publisher Link]

[42] Chamak Ganguly et al., “Design and Analysis of a New Ultra Low Power Adiabatic VLSI Circuit,” Journal of VLSI Design and Signal Processing, vol. 9, no. 2, pp. 1-12, 2023. 
[Google Scholar] [Publisher Link]

[43] Chamak Ganguly et al., “Analysis of a Low-Power Full Adder and Half Adder using a New Adiabatic Logic,” 2023 26^th International Conference on Computer and Information Technology (ICCIT), Cox's Bazar, Bangladesh, pp. 1-5, 2023.
[CrossRef] [Google Scholar] [Publisher Link]

[44] C. Venkatesh, A. Mohanapriya, and R. Sudha Anandhi, “Performance Analysis of Adiabatic Techniques using Full Adder for Efficient Power Dissipation,” ICTACT Journal on Microelectronics, vol. 4, no. 1, pp. 510-514, 2018. 
[Google Scholar] [Publisher Link]

[45] K.W. Ng, and K.T. Lau, “Low Power Flip-Flop Design based on PAL-2N Structure,” Microelectronics Journal, vol. 31, no. 2, pp. 113-116, 2000.
[CrossRef] [Google Scholar] [Publisher Link]

[46] Jianping Hu, Tiefeng Xu, and Yinshui Xia, “Low-Power Adiabatic Sequential Circuits with Complementary Pass-Transistor Logic,” 48^th Midwest Symposium on Circuits and Systems, 2005, Covington, KY, USA, vol. 2, pp. 1398-1401, 2005.
[CrossRef] [Google Scholar] [Publisher Link]

[47] Haiyan Ni, and Jianping Hu, “Single-Phase Adiabatic Flip-Flops and Sequential Circuits with Power-Gating Scheme,” 2009 IEEE 8^th International Conference on ASIC, Changsha, China, pp. 879-882, 2009.
[CrossRef] [Google Scholar] [Publisher Link]

[48] A. Parveen, and Thamarai Selvi, “Power Efficient Design of Adiabatic Approach for Low Power VLSI Circuits,” 2019 Fifth International Conference on Electrical Energy Systems (ICEES) 2019, Chennai, India, pp. 1-4, 2019.
[CrossRef] [Google Scholar] [Publisher Link]

[49] Y. Syamala, and K. Srilakshmi, “Adiabatic Multiplexer and Delay Flip-Flop,” International Conference on Advances in Electrical and Computer Technologies, pp. 715-725, 2022.
[CrossRef] [Google Scholar] [Publisher Link]

[50] Changning Luo, and Jianping Hu, “Single-Phase Adiabatic Flip-Flops and Sequential Circuits using Improved CAL Circuits,” 2007 7^th International Conference on ASIC, Guilin, China, pp. 126-129, 2007.
[CrossRef] [Google Scholar] [Publisher Link]

[51] K.W. Ng, and K.T. Lau, “ECRL-based Low Power Flip-Flop Design,” Microelectronics Journal, vol. 31, no. 5, pp. 365-370, 2000.
[CrossRef] [Google Scholar] [Publisher Link]

[52] Naga Raju Jangam, Likhitha Guthikinda, and G.P. Ramesh, Design and Analysis of New Ultra Low Power CMOS based Flip-Flop Approaches,” Distributed Computing and Optimization Techniques, pp. 295-302, 2022.
[CrossRef] [Google Scholar] [Publisher Link]

[53] Rene Celis-Cordova et al., “Adiabatic Flip-Flop and SRAM Design for an Adiabatic Reversible Microprocessor,” 2020 International Conference on Rebooting Computing (ICRC), Atlanta, GA, USA, pp. 9-15, 2020.
[CrossRef] [Google Scholar] [Publisher Link]

[54] B.P. Bhuvana, B.R. Manohar, and V.S. kanchana Bhaaskaran, “Adiabatic Logic Circuits using FinFETs and CMOS - A Review,” International Journal of Engineering and Technology, vol. 8, no. 2, pp. 1256-1270, 2016.
[Google Scholar]

[55] Christopher L. Ayala et al., “Multi-GHz Zeptojoule Computing using Emerging Adiabatic Superconductor Circuits,” 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Knoxville, TN, USA, pp. 557-564, 2024.
[CrossRef] [Google Scholar] [Publisher Link]

[56] Mengmeng Wang, Olivia Chen, and Nobuyuki Yoshikawa, “A Neural Network Processing Unit using Adiabatic Quantum-Flux-Parametron Superconducting Technology,” 2022 IEEE 11^th Global Conference on Consumer Electronics (GCCE), Osaka, Japan, pp. 111-113, 2022.
[CrossRef] [Google Scholar] [Publisher Link]

[57] Zhengang Li et al., “SupeRBNN: Randomized Binary Neural Network using Adiabatic Superconductor Josephson Devices,” Proceedings of the 56^th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 584-598, 2023.
[CrossRef] [Google Scholar] [Publisher Link]

[58] Manoj Sharma, and Arti Noor, “Reconfigurable CPL Adiabatic Gated Logic RCPLAG based Universal NAND/NOR Gate,” International Journal of Computer Applications, vol. 95, no. 26, pp. 27-32, 2014.
[CrossRef] [Google Scholar] [Publisher Link]

[59] Manoj Sharma, and Arti Noor, “Reconfigurable CPLAG and Modified PFAL Adiabatic Logic Circuits,” Advances in Electronics, vol. 2015, pp. 1-10, 2015.
[CrossRef] [Google Scholar] [Publisher Link]

[60] A. Kishore Kumar et al., “Low Power Multiplier Design using Complementary Pass-Transistor Asynchronous Adiabatic Logic,” International Journal on Computer Science and Engineering, vol. 2, no. 7, pp. 2291-2297, 2010.
[Google Scholar]

[61] Himadri Singh Raghav, “Adiabatic Circuits for Power-Constrained Cryptographic Computations,” PhD Thesis, University of Westminster Computer Science and Engineering, 2018.
[CrossRef] [Google Scholar] [Publisher Link]

[62] Jheng-Sin Liu, “Advanced Energy-Efficient Devices for Ultra-Low Voltage System: Materials-to-Circuits,” Doctoral Dissertations, Virginia Tech, 2018.
[Google Scholar] [Publisher Link]

[63] Sandeep Miryala, “CAD Solutions for Graphene based Nanoelectronic Circuits and Systems,” Doctoral Thesis Polito, 2014.
[Google Scholar] [Publisher Link]

[64] Yitao Fan et al., “Global Research on Nanomaterials for Liver Cancer from 2004 to 2023: A Bibliometric and Visual Analysis,” Discover Oncology, vol. 15, no. 1, pp. 1-37, 2024.
[CrossRef] [Google Scholar] [Publisher Link]

[65] Naveen Donthu et al., “How to Conduct a Bibliometric Analysis: An Overview and Guidelines,” Journal of Business Research, vol. 133, pp. 285-296, 2021.
[CrossRef] [Google Scholar] [Publisher Link]

[66] Chaomei Chen, “Searching for Intellectual Turning Points: Progressive Knowledge Domain Visualization,” Proceedings of the National Academy of Sciences, vol. 101, no. suppl_1, pp. 5303-5310, 2000.
[CrossRef] [Google Scholar] [Publisher Link]

[67] Nees van Eck, and Ludo Waltman, “Software Survey: VOSviewer, a Computer Program for Bibliometric Mapping,” Scientometrics, vol. 84, no. 2, pp. 523-538, 2010.
[CrossRef] [Google Scholar] [Publisher Link]

[68] Mathieu Bastian, Sebastien Heymann, and Mathieu Jacomy, “Gephi: An Open Source Software for Exploring and Manipulating Networks,” Proceedings of the International AAAI Conference on Web and Social Media, vol. 3, no. 1, pp. 361-362, 2009.
[CrossRef] [Google Scholar] [Publisher Link]

[69] Jasleen Kaur et al., “Scholarometer: A Social Framework for Analyzing Impact Across Disciplines,” PLoS One, vol. 7, no. 9, pp. 1-13, 2012, 
[CrossRef] [Google Scholar] [Publisher Link]

[70] Massimo Aria, and Corrado Cuccurullo, “Bibliometrix: An R-Tool for Comprehensive Science Mapping Analysis,” Journal of Informetrics, vol. 11, no. 4, pp. 959-975, 2017.
[CrossRef] [Google Scholar] [Publisher Link]

[71] Fenglin Zuo et al., “Research on Wildfire and Soil Water: A Bibliometric Analysis from 1990 to 2023,” Fire, vol. 7, no. 12, pp. 1-14, 2024.
        [CrossRef] [Google Scholar] [Publisher Link]