Implementation of Turbo Encoder and Decoder

	International Journal of Engineering Trends and Technology (IJETT)
	© 2014 by IJETT Journal
	Volume-8 Number-2
	Year of Publication : 2014
	Authors : Mrs.K.M.Bogawar , Ms.Sharda Mungale , Dr.Manish Chavan
	10.14445/22315381/IJETT-V8P214

Citation

Mrs.K.M.Bogawar , Ms.Sharda Mungale , Dr.Manish Chavan."Implementation of Turbo Encoder and Decoder", International Journal of Engineering Trends and Technology(IJETT), 8(2),73-76 February 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

Turbo code has become the coding technique of choice in many communication and storage systems due to its near Shannon limit error correction capability. With requirement on increasing data rates for deep space mission, it is required to have efficient encoder and decoder. Turbo codes provide up to 0.8 dB improvement in Eb/No over the current best codes used by deep space missions. The total number of decoder iterations depends on the physical channel characteristics. In this paper, we proposed a turbo encoder with the 1/3,1/4,1/6 rate and turbo decoder.

References

[1] By Kenneth S. Andrews, Dariush Divsalar, Sam Dolinar “The Development of Turbo and LDPC Codes for Deep-Space Applications” IEEE | Vol. 95, No. 11, November 2007
[2] ”Development Plan for Turbo Encoder Core and Devices Implementing the Updated CCSDS Telemetry Channel Coding Standard” ,Sandi Habinc,Gian Paolo Calzolari,Enrico Vassallo
[3] ” Comparison and Analysis of ECSS based Turbo Decoder Stopping Rules” Adnan Aslam Chaudhry, Mussadiq Ali Shah, 2012 IEEE
[4] ”Parallel Interleaver Design and VLSI Architecture for Low-Latency MAP Turbo Decoders” Rostislav (Reuven) Dobkin, Michael Peleg, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO.pp.427-438, APRIL 2005
[5] “VHDL Implementation of a Turbo Decoder With Log-MAP-Based Iterative Decoding” Yanhui Tong, Tet-Hin Yeap, Member, IEEE, and Jean-Yves Chouinard, Senior Member, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 4,pp.1268-1278, AUGUST 2004
[6] ” VLSI Architectures for Turbo Decoding Message Passing Using Min-Sum for Rate-Compatible Array LDPC Codes” Kiran Gunnam, Weihuang Wang, Gwan Choi, Mark Year, 2007 IEEE
[7] ” PARALLEL VLSI ARCHITECTURE FOR MAP TURBO DECODER” Rnstislav (Reuven) Dnbkin, Michael Peleg, Ran Ginnsar,pp.384-388,2002 IEEE

Keywords
Turbo coding, forward error correction, interleaving, puncturing, iterative decoding, MAP decoding.

IJBTT

Implementation of Turbo Encoder and Decoder