IJBTT

Development of FPGA based Human Voice Recognition System with MFCC feature

	International Journal of Engineering Trends and Technology (IJETT)
	© 2014 by IJETT Journal
	Volume-8 Number-10
	Year of Publication : 2014
	Authors : Mr. Anand Mantri , Mr. Mukesh Tiwari , Mr. Jaikaran Singh
	10.14445/22315381/IJETT-V8P297

Citation 

Mr. Anand Mantri , Mr. Mukesh Tiwari , Mr. Jaikaran Singh. "Development of FPGA based Human Voice Recognition System with MFCC feature", International Journal of Engineering Trends and Technology(IJETT), V8(10),546-550 February 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

The voice recognition development on the hardware is also a challenging field due to minimal hardware resource utilization with higher accuracy demand. This paper described the FPGA based human voice recognition system. This system includes voice activity detection, MFCC feature extraction, HMM filter generation and classification of voice. The system is train for different person with the repeated voice for achieving the higher accuracy. The HMM filter coefficient for different person is only stored for reducing the memory utilization. The standard FFT and DCT blocks are used to reduce the hardware utilization. The development results are given in this paper for illustrating the effectiveness of system.

References

[1] X. Zhu, Y. Chen, J. Liu, R. Liu, ”A Novel Efficient Decoding Algorithm.For CDHMM-based Speech Recognizer on Chip.” Proc. of IEEE ICA-SSP, 2003.
[2] M. Yuan, T. Lee, P. C. Ching, Y. Zhu, ”Speech Recognition on DSP:Issues on Computational Efficiency and Performance Analysis ”Proc. Of IEEE ICCCAS, 2005.
[3] Zh. Yang, J. Liu, E. Chan, L. Guan, Ch. Ching, ”DSP-based Systemon-Chip Moves Speech Recognition from the Lab to Portable Devices”,www.embedded.com, Jan 2007.
[4] S. Yoshizawa, N.Wada, N. Hayasaka, Y. Miyanaga, ”Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system”. IEEE Trans. on Circuits and Systems I, Vol. 53, No. 1, Jan 2006, pp. 70-77.
[5] M. Yuan, T. Lee, P. C. Ching, and Y. Zhu, “Speech recognition on DSP: Issues on computational efficiency and performance analysis,” in Proc. IEEE ICCCAS, 2005, pp. 852–856.
[6] S. Dobler, “Speech recognition technology for mobile phones,” Ericsson Rev., vol. 77, no. 3, pp. 148–155, 2000.
[7] [Online]. Available: http://www.sensoryinc.com
[8] [Online]. Available: http://www.voicecontrol.com
[9] [Online]. Available: http://www.voicegate.com/voiceics.htm
[10] P. Placeway, et al, “The 1996 HUB-4 Sphinx-3 System”, Proc. DARPA Speech Recognition Workshop, Feb. 1997.
[11] K.K. Agaram, S.W. Keckler, D. Burger, “Characterizing the SPHINX Speech Recognition System”, University of Texas at Austin, Department of Computer Sciences, Technical Report TR2001-18, January 2001.
[12] J. Pihl, T. Svendsen, and M. H. Johnsen, “A VLSI implementation of pdf computations in HMM based speech recognition,” in Proc. IEEE TENCON’96, 1996, pp. 241–246
[13] W. Han, K. Hon, and C. Chan, “An HMM-based speech recognition IC,” in Proc. IEEE ISCAS’03, vol. 2, 2003, pp. 744–747.
[14] S. J. Melnikoff, S. Quigley, and M. J. Russell, “Implementing a simple continuous speech recognition system on an FPGA,” in Proc. IEEE Symp. FPGAs for Custom Computing Machines (FCCM’02), 2002, pp. 275–276.
[15] F. Vargas, R. Fagundes, and D. Barros, “A FPGA-based Viterbi algorithm implementation for speech recognition systems,” in Proc. IEEE ICASSP’01, vol. 2, May s2001, pp. 1217–1220.
[16] L. R. Rabiner, “Recognition of isolated digits using hidden Markov models with continuous mixture densities,” AT&T Tech. J., vol. 64, no. 6, pp. 1211–1234, 1985.
[17] M. Karnjanadecha and S. A. Zahorian, “Signal modeling for isolated word recognition,” in Proc. IEEE ICASSP’99, vol. 1, Mar. 1999, pp. 293–296.
[18] U. C. Pazhayaveetil, “Hardware implementation of a low power speech recognition system,” Ph.D. dissertation, Dept. Elect. Eng., North Carolina State Univ., Raleigh, NC, 2007.
[19] S. Nedevschi, R. K. Patra, and E. A. Brewer, “Hardware speech recognition
[20] for user interfaces in lowcost, lowpower devices,” in Proc. IEEE DAC, 2005, pp. 684–689.
[21] W. Han, K. Hon, Ch. Chan, T. Lee, Ch. Choy, K. Pun, and P. C. Ching, “An HMM-based speech recognition IC,” in Proc. IEEE ISCAS, 2003, pp. 744–747.
[22] R. Krishna, S. Mahlke, and T. Austin, “Architectural optimizations for low-power, real-time speech recognition,” in Proc. ACMCASES, 2003, pp. 220–231.

Keywords
FPGA, Voice Recognition, MFCC (Mel-Frequency Cepstral Coefficients), HMM (Hidden Markov Model), VAD (Voice Activity Detection), LPC.