32 Bit Parallel Multiplier Using VHDL

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-9 Number-3                          
Year of Publication : 2014
Authors : Vrushali Gaikwad , Rajeshree Brahmankar , Amiruna Warambhe , Yugandhara Kute , Nishant Pandey


Vrushali Gaikwad , Rajeshree Brahmankar , Amiruna Warambhe , Yugandhara Kute , Nishant Pandey. "32 Bit Parallel Multiplier Using VHDL", International Journal of Engineering Trends and Technology(IJETT), V9(3),129-132 March 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group


In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. Here comparison is done between Carry Save Adder (CSA) and Carry Look Ahead Adder (CLA). The comparison is done on the basis of two performance parameters i.e. Speed and Power consumption. To design an efficient integrated circuit in terms of power and speed, has become a challenging task VLSI design field.


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Multiplier, Carry Save adder(CSA), Carry Look Ahead adder(CLA), Ripple Carry Adder(RCA), VHDL simulation.