32 Bit Parallel Multiplier Using VHDL
Vrushali Gaikwad , Rajeshree Brahmankar , Amiruna Warambhe , Yugandhara Kute , Nishant Pandey. "32 Bit Parallel Multiplier Using VHDL", International Journal of Engineering Trends and Technology(IJETT), V9(3),129-132 March 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. Here comparison is done between Carry Save Adder (CSA) and Carry Look Ahead Adder (CLA). The comparison is done on the basis of two performance parameters i.e. Speed and Power consumption. To design an efficient integrated circuit in terms of power and speed, has become a challenging task VLSI design field.
 B. Parhami, Computer Arithmetic, Algorithm and Hardware Design, Oxford University Press, New York, pp. 91-119, 2000.
 Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design.2nd Edn. McGraw-Hill Higher Education, USA.ISBN: 0072499389, 2005.
 Wakerly, J.F., 2006. Digital Design-Principles and Practices. 4th Edn. Pearson Prentice Hall, USA.ISBN: 0131733494.
 Rajender Kumar, Sandeep Dahiya, “Performance Analysis of Different Bit Carry Look Ahead Adder Using VHDL Environment, International Journal of Engineering Science and Innovative Technology (IJESIT)”, Volume 2, Issue 4, July 2013. ISSN: 2319-5967.
 A. Sertbas and R.S. Özbey, “A performance analysis of classified binary adder architectures and the VHDL simulations”, J. Elect. Electron. Eng., Istanbul, Turkey, vol. 4, pp. 1025-1030, 2004.
 Raminder Preet Pal Singh, Parveen Kumar, Balwinder Singh, “Performance Analysis of 32-Bit Array Multiplier with a Carry Save Adder and with a Carry-Look-Ahead Adder”, International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009.
 Hasan Krad and Aws Yousif, “Design and Implementation of a Fast Unsigned 32-bit Multiplier Using VHDL”
 Hasan Krad and Aws Yousif Al-Taie, “Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL”, Journal of Computer Science 4 (4): 305-308, 2008
 Fonseca, M.; da Costa, E. et al, “Design of a Radix-2m Hybrid Array Multiplier Using Carry Save Adder” integrated Circuits and System Design, 18th Symposium on Volume, Issue, 4-7 Sept. 2005 Page(s): 172-177.
Multiplier, Carry Save adder(CSA), Carry Look Ahead adder(CLA), Ripple Carry Adder(RCA), VHDL simulation.