A Survey on Leakage Power Reduction Techniques by Using Power Gating Methodology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2014 by IJETT Journal
Volume-9 Number-11                          
Year of Publication : 2014
Authors : Pramod Kumar. M.P , A.S. Augustine Fletcher
  10.14445/22315381/IJETT-V9P308

MLA 

Pramod Kumar. M.P , A.S. Augustine Fletcher. "A Survey on Leakage Power Reduction Techniques by Using Power Gating Methodology", International Journal of Engineering Trends and Technology (IJETT), V9(11),566-571 March 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

As the technology moves into deep sub-micron region, the power consumption of the integrated circuit will be more. In the current technologies, the leakage power is the major part in the total power consumption. Power gating is a technique which is used to reduce the leakage power by shutting off the idle logic blocks using sleep transistors. Different power gating methods are available now. These helps in reducing the power, delay and switching time of the logics. This survey paper mentions some important power gating techniques and its comparison.

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Keywords
CMOS, MTCMOS, power gating, threshold voltage, sleep mode etc.