Area Reduction of Test Pattern Generation Used in BIST Schemes
International Journal of Engineering Trends and Technology (IJETT) | |
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© 2014 by IJETT Journal | ||
Volume-9 Number-13 |
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Year of Publication : 2014 | ||
Authors : Nandini Priya.M |
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10.14445/22315381/IJETT-V9P330 |
Citation
Nandini Priya.M. "Area Reduction of Test Pattern Generation Used in BIST Schemes", International Journal of Engineering Trends and Technology (IJETT), V9(13),687-693 March 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
This paper proposes a test pattern generator (TPG) for built-in-self-test. This method generates Multiple Single Input Change Vector (MSIC), which in turn are applied to the scan chain. The existing methodology uses Johnson counter, xor gate and LFSR for generating Multiple Single Input Change Vector. But the drawback of the previous technique was more Area consumption. Hence in order to reduce the area Multiple Single Input Change Vectors are generated using Johnson counter and Accumulator. This test pattern generation technique for BIST schemes is coded using VHDL and simulated using ModelSim 10.0b. The gate count and power required for test pattern generation is analyzed using Xilinx ISE 9.1 software.
References
[1] Y. Zorian, ‘A distributed BIST control scheme for complex VLSI devices,’ proceedings of 11th Annual IEEE VLSI Test Symposium Digital Papers, April 1993, pp. 4–9.
[2] P. Girard, ‘Survey of low-power testing of VLSI circuits,’ IEEE Design Test Comput., vol. 19, no. 3, pp. 80–90, May–June 2002.
[3] A. Abu-Issa and S. Quigley, ‘Bit-swapping LFSR and scan-chain ordering: A novel technique for peak- and average-power reduction in scan-based BIST,’ IEEE Trans. Computer-Aided Design Integrated Circuits System , vol. 28, no. 5, pp. 755–759, May 2009.
[4] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, and M. Santos, ‘Low-energy BIST design: Impact of the LFSR TPG parameters on the weighted switching activity,’ Proceedings of IEEE International Symposium Circuits System, vol. 1. Jul. 1999, pp. 110–113.
[5] S. Wang and S. Gupta, ‘DS-LFSR: A BIST TPG for low switching activity,’ IEEE Transaction Computer Aided Design Integrated Circuits System, vol. 21, no. 7, pp. 842–851, July 2002.
[6] F. Corno, M. Rebaudengo, M. Reorda, G. Squillero, and M. Violante, ‘Low power BIST via non -linear hybrid cellular automata,’ Proceedings of 18th IEEE VLSI Test Symposium, April–May 2000, pp. 29–34.
[7] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. Wunderlich, ‘A modified clock scheme for a low power BIST test pattern generator,’ Proceedings of 19th IEEE VTS VLSI Test Symposium , March–April 2001, pp. 306–311.
[8] D. Gizopoulos, N. Krantitis, A. Paschalis, M. Psarakis, and Y. Zorian, ‘Low power/energy BIST scheme for datapaths,’ proceedings of 18th IEEE VLSI Test Symposium, April–May 2000, pp. 23–28.
[9] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, ‘A gated clock scheme for low power scan testing of logic ICs or embedded cores,’ proceedings of 10th Asian Test Symposium, November 2001, pp. 253–258.
[10] C. Laoudias and D. Nikolos, ‘A new test pattern generator for high defect coverage in a BIST environment,’ proceedings of 14th ACM Great Lakes Symposium VLSI, April 2004, pp. 417–420.
[11] S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, ‘Low-power scan design using first-level supply gating,’ IEEE Transaction Very Large Scale Integrated (VLSI) System, vol. 13, no. 3, pp. 384–395, March 2005.
[12] X. Kavousianos, D. Bakalis, and D. Nikolos, ‘Efficient partial scan cell gating for low-power scan-based testing,’ ACM Trans. Design Automation Electronic System, vol. 14, no. 2, pp. 28-1–28-15, March 2009.
Keywords
Built-in-self-test (BIST), Multiple Single Input Change Vector (MSIC), Test Pattern Generator (TPG).