Area Reduction of Test Pattern Generation Used in BIST Schemes
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2014 by IJETT Journal|
|Year of Publication : 2014|
|Authors : Nandini Priya.M
Nandini Priya.M. "Area Reduction of Test Pattern Generation Used in BIST Schemes", International Journal of Engineering Trends and Technology (IJETT), V9(13),687-693 March 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
This paper proposes a test pattern generator (TPG) for built-in-self-test. This method generates Multiple Single Input Change Vector (MSIC), which in turn are applied to the scan chain. The existing methodology uses Johnson counter, xor gate and LFSR for generating Multiple Single Input Change Vector. But the drawback of the previous technique was more Area consumption. Hence in order to reduce the area Multiple Single Input Change Vectors are generated using Johnson counter and Accumulator. This test pattern generation technique for BIST schemes is coded using VHDL and simulated using ModelSim 10.0b. The gate count and power required for test pattern generation is analyzed using Xilinx ISE 9.1 software.
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Built-in-self-test (BIST), Multiple Single Input Change Vector (MSIC), Test Pattern Generator (TPG).