Low Power Full Adder With Reduced Transistor Count

Low Power Full Adder With Reduced Transistor Count

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2013 by IJETT Journal
Volume-4 Issue-5                      
Year of Publication : 2013
Authors : M.Geetha Priya , K.Baskaran

Citation 

M.Geetha Priya , K.Baskaran . "Low Power Full Adder With Reduced Transistor Count". International Journal of Engineering Trends and Technology (IJETT). V4(5):1755-1759 May 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.

Abstract

Basic building blocks of most of the arithmetic and logic circuits are formed by XOR logic gate. This paper proposes a new 3T - XOR gate with significant area and power savings. In most of the digital systems adder lies in the critical path that increases the overall computational delay of the system. A new eight transistors one bit full adder based on 3T - XOR gate is presented. Simulations results utilizin g standard 90nm CMOS technology illustrate a significant improvement in terms of number of transistors, chip area and propagation delay.

References

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Keywords
Full adder, CMOS, PDP, Pass transistor, XOR , low power.