Design & Implementation Of 32-Bit Risc (MIPS) Processor
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2013 by IJETT Journal|
|Year of Publication : 2013|
|Authors : Marri Mounika , Aleti Shankar|
Marri Mounika , Aleti Shankar. "Design & Implementation Of 32-Bit Risc (MIPS) Processor ". International Journal of Engineering Trends and Technology (IJETT). V4(10):4466-4474 Oct 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.
In this paper we propose a novel technique of run-time loading of machine code for MIPS-32 soft-core processor. As we know, implementing fewer instructions and addressing modes on silicon reduces the complexity of the instruction decoder, the addressing logic, and the execution unit. This allows the machine to be clocked at a faster speed, since less work needs to be done each clock period. Our proposed RISC MIPS Processor technique sends the machine code to the instruction memory of the soft-core from the software tool through UART. The user should use that software tool to write MIPS assembly code, debug the code and generate the machine code. Also, the software tool is used for establishing UART connection.
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MIPS, Data Flow, Data Path, Pipeline, RISC, CISC.