A Survey on Leakage Power Reduction Techniques by Using Power Gating Methodology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-9 Number-11                          
Year of Publication : 2014
Authors : Pramod Kumar. M.P , A.S. Augustine Fletcher


Pramod Kumar. M.P , A.S. Augustine Fletcher. "A Survey on Leakage Power Reduction Techniques by Using Power Gating Methodology", International Journal of Engineering Trends and Technology (IJETT), V9(11),566-571 March 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group


As the technology moves into deep sub-micron region, the power consumption of the integrated circuit will be more. In the current technologies, the leakage power is the major part in the total power consumption. Power gating is a technique which is used to reduce the leakage power by shutting off the idle logic blocks using sleep transistors. Different power gating methods are available now. These helps in reducing the power, delay and switching time of the logics. This survey paper mentions some important power gating techniques and its comparison.


[1] Suhwan Kim, Stephen V. Kosonocky, and Daniel R. Knebel, “Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures,” Proceedings of the IEEE International Symposium on Low Power Electronics and Design (ISLPED), pp.22 – 25, 25-27 Aug. 2003.
[2] A. Sathanur, A. Calimera, A. Pullini, L. Benini, A. Macii, E. Macii, M.Poncino, “On Quantifying the Figures of Merit of Power Gating for Leakage Power Minimization in Nanometer CMOS Circuits,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2761 – 2764, 18-21 May 2008.
[3] Harmander Singh, Kanak Agarwal, Dennis Sylvester, and Kevin J. Nowka, “Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 11, pp.12-15, November 2007.
[4] Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, and Marios C. Papaefthymiou, “A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs,” IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 7, July 2007.
[5] K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, “16.7-fa/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierros,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1952–1957, Nov. 2003.
[6] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murry, N. Vallepalli, Y.Wang, B. Zheng, and M. Bohr, “SRAM design on 65nm CMOS technology with dynamic sleep transistor for leakage reduction,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 895–901, Apr. 2005.
[7] M. Anis, S. Areibi, M. Mahmoud and M. Elmasry, “Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique,” Design Automation Conf., pp. 480-485, 2002.
[8] J.Kao et al., “MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns,” Proc. of the 35th DAC, pp. 495–500, 1998.
[9] Ashoka. Sathanur, Benini.L, Macii.A, Macii.E and Poncino.M, “Row-Based Power Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometre CMOS Circuits,” IEEE Trans. VLSI Syst., vol. 19, no.3, pp. 469–482, 2011.
[10] Afshin Abdollahi, Farzan Fallah, and Massoud Pedram, “A robust power gating structure and power mode transition strategy for MTCMOS design,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 15.1, pp. 80-89, Jan. 2007.
[11] J. Kao, S. Narenda and A. Chandrakasan, “MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns,” Design Automation Conf., pp. 495 - 500, 1998.
[12] S. Kosonocky, M. Immediato, P. Cottrell, T. Hook, R. Mann, and J. Brown, “Enhanced multi-threshold (MTCMOS) circuits using variable well bias,” ISLPED, pp. 165-169, Aug.2001.
[13] Yuan Taur; Tak. H. Ning, Fundemental of Modern VLSI Devices, Cambridge University Press. Cambridge, 1998. [14] Divya.R, Muralidharan.J, “Leakage Power Reduction through Hybrid Multi-Threshold CMOS Stack Technique in Power Gating Switch,” IJARCET, pp.1614-1618, 2013.
[15] Ehsan Pakbaznia and Massoud Pedram, “Design of a Tri-Modal Multi- Threshold CMOS switch with application to to Data Retentive Power Gating,” IEEE transactions on VLSI systems., vol. 20, no. 2, pp.380–385, February 2012.
[16] K. Usami, N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa, “Automated selective multi-threshold design for ultra-low standby applications,” in Proc. ACM/IEEE Int. Symp. Low Power Electron. Des. (ISLPED), Monterey, CA, pp. 202–206, Aug. 2002.
[17] Kanak Agarwal, Harmander Deogun , Dennis Sylvester and Kevin Nowka, “Power Gating with Multiple Sleep Modes,” IEEE Proceedings of the International Symposium on Quality Electronic Design (ISQED), pp 633-637, 27-29 March 2006.
[18] Pramod Kumar.M.P and A.S.Augustine Fletcher, “A Novel Hybrid Multiple Mode Power Gating,” IEEE International Conference on Electronics and Communication System (ICECS’14), Feb.13-14, 2014.
[19] S. Anvesh and P. Raman Reddy, “Optimized Design of an ALU Block Using Power Gating Technique,” IOSR Journal of Electronics and Communication Engineering (IOSR-JECE), Volume 4, Issue2, pp.24-30, Sep. 2011.
[20] Pramod Kumar M.P., A.S. Augustine Fletcher, “Power gating in 8 bit ALU: A comparative study,” International Conference on Recent Innovations in Engineering (ICRIE ‘14), March 13-14, 2014.

CMOS, MTCMOS, power gating, threshold voltage, sleep mode etc.