Comparative Analysis of 1-Bit Adiabatic Full Subtractor Designed in 45nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-10 Number-11
Year of Publication : 2014
Authors : Nikhil Deo , Rusni Kima Mangang


Nikhil Deo , Rusni Kima Mangang. "Comparative Analysis of 1-Bit Adiabatic Full Subtractor Designed in 45nm Technology", International Journal of Engineering Trends and Technology (IJETT), V10(11),541-544 April 2014. ISSN:2231-5381. published by seventh sense research group


This paper presents a comparative analysis of a 1-bit adiabatic full subtractor designed in 45nm technology node. Adiabatic logic is a low power digital circuit design technique which is much more power efficient than CMOS logic. We designed 1-bit full subtractor using 2N2N2P and DCPAL adiabatic logic styles which are two of the popular adiabatic logic styles. We found that the full subtractor designed using DCPAL saves much more power than 2N2N2P adiabatic logic style, also we simulated our circuits at two different frequencies of 100MHz and 300MHz.


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Adiabatic logic, 2N2N2P, DCPAL, low power