An Area Efficient (31, 16) BCH Decoder for Three Errors
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2014 by IJETT Journal|
|Year of Publication : 2014|
|Authors : M. Prashanthi , P. Samundiswary
M. Prashanthi , P. Samundiswary. "An Area Efficient (31, 16) BCH Decoder for Three Errors", International Journal of Engineering Trends and Technology (IJETT), V10(13),616-620 April 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Bose, Ray- Chaudhuri, Hocquenghem (BCH) codes are one of the efficient error-correcting codes used to correct errors occurred during the transmission of the data in the unreliable communication mediums. This paper presents a low-complexity and area efficient error-correcting BCH decoder architecture for detecting and correcting three errors. The advanced Peterson error locator computation algorithm, which significantly reduces computational complexity, is proposed for the IBM block in the (31,6) BCH decoder. In addition, a modified syndrome calculator and chien search are proposed to reduce hardware complexity. The design methodologies of the proposed BCH decoder models have considerably less hardware complexity and latency than those using conventional algorithms. The proposed (31, 16) BCH decoder over GF (5), leads to a reduction in complexity compared to that of conventional BCH decoder. The enhanced BCH decoder is designed using hardware description language called Verilog and synthesized in Xilinx ISE 13.2.
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BCH decoder, Peterson’s algorithm, chien Search, VLSI design.