High Secured and Fault Tolerant Errorless Communication for Low Power Asynchronous Applications

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-13 Number-8                          
Year of Publication : 2014
Authors : R. Himaneesh Yadav , I. Saidulu


R. Himaneesh Yadav , I. Saidulu . "High Secured and Fault Tolerant Errorless Communication for Low Power Asynchronous Applications", International Journal of Engineering Trends and Technology (IJETT), V13(8),351-355 July 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group


This enhanced project design a fully fault-tolerant memory architecture that is capable of tolerating hardware or software errors not only in the memory bits but also in the supporting logic including the ECC encoder and corrector with low power consumption and more security. This project uses a Euclidean Geometry codes, SEA (Scalable Encryprion Algorithm). Hence proved that these codes are part of a new subset of ECCs that have FSDs. Using these FSDs we design a fault-tolerant encoder and corrector with more security, where the fault-secure detector monitors The parity-check Matrix of an FSD-ECC(fault secure detector - error correcting code) has a particular structure that the decoder circuit, generated from the parity-check Matrix, is Fault-Secure. LDPC codes satisfies a new, restricted definition for ECCs which guarantees that the ECC codeword has an appropriate redundancy structure such that it can detect multiple errors occurring in both the stored codeword in memory and the surrounding circuitries.


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