Design of a Low Voltage Class-AB CMOS Super Buffer Amplifier with Sub Threshold and Leakage Control

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-7 Number-1                          
Year of Publication : 2014
Authors :Rakesh Gupta


 Rakesh Gupta.Article:Design of a Low Voltage Class-AB CMOS Supper Buffer Amplifier with Sub Threshold and Leakage Control, International Journal of Engineering Trends and Technology (IJETT), V7(1):13-17;January 2014. Published by Seventh Sense Research Group.


This paper describes a CMOS analogy voltage supper buffer designed to have extremely low static current Consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation. The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the reduced low power dissipation (1.105%), low leakage and reduced area (3.08%) also. The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3.3V supply[11]. Consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and Design automation techniques to accomplish this goal [9].


[1]    C.-C. Wang And J.-C. Wu, “A 3.3-V/5-V Low Power Ttl-To-Cmos Input Buffer”, Ieee Journal Of Solid-State Circuits, Vol. 33, No. 4, (1998).
[2]    Y. Taur And T. H. Ning, Fundamentals Of Modern VlsiDevices,New York, Usa: Cambridge University Press, 1998, Ch. 3, Pp.120-128.
[3]    Mutoh, S., Douskei, T., Matsuya, Y., Aoki, T., Shigematsu, S. and Yamada J., “1-V Power Supply High-Speed Digital Circuit Technology with Multi-threshold Voltage CMOS,” IEEE Journal of Solid-state Circuits, Aug. 1995, pp. 847- 854.
[4]    Kuroda, T., et. al., “A 0.9V 150MHz 10mW 4mm2 2-D discrete cosine transform core processor with variable threshold voltage (VT) scheme,” IEEE Journal of Solid-State Circuits, Nov. 1996, pp. 1770-1779.
[5]    Assaderaghi, F., Sinitsky, D., Parke, S.A., Bokor, J., Ko, P.K. and Hu, C., “Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Transactions on Electron Devices, Vol. 44, No. 3, Mar. 1997, pp. 414 – 422.
[6]    Abdollahi, A., Fallah, F., and Pedram, M., “Runtime mechanisms for leakage current reduction in CMOS VLSI circuits,” Proc. of Symp. on Low Power Electronics and Design, Aug. 2002, pp. 213-218.
[7]     Bobba, S. and Hajj, I., “Maximum Leakage Power Estimation for CMOS Circuits,” Proc. of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999, pp. 116 – 124.
[8]     Vijay Kumar Sharma &SurenderSoni, “Comparison among different CMOS inverter for Low leakage at different Technologies, ” International journal of applied engineering research,Dindigul ,Volume 1, No 2, 2010.
[9]     M. Aloito and G. Palumbo, “Power Aware Design of Nanometer MCML Tapered Buffer”, IEEE Transactions on circuits and systems-II: Express Briefs, vol. 55, no. 1, (2008).
[10]     T. Saether, C.-C. Hung, Z. Qi, M. Ismail and O Aaserud, “High Speed, High Linearity CMOS Buffer Amplifier”, IEEE Journal of Solid-State Circuits, vol. 31, no. 2, (1996).
[11]     K. Nang Leung and Y. Sum Ng, “A CMOS Low Dropout Regulator with a momentarily current-Boosting voltage Buffer”, IEEE Transactions on circuits and systems-I: Regular paper, vol. 57, no. 9, (2010).
[12]     C.-W. Lu, P.-Y.-Y. Kuo, H.-Lun and S. Pennisi, “A Low Quiescent Current Two Input-Output buffer amplifier for LCDs”, IEEE Transaction, (2012).

Keywords —Class AB buffer, low-voltage, leakage power , threshold Current.