A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2015 by IJETT Journal|
|Year of Publication : 2015|
|Authors : Mrs. KIRUTHIKA.S.V, Dr. (Mrs.) R. SUDARMANI
|DOI : 10.14445/22315381/IJETT-V22P207|
Mrs. KIRUTHIKA.S.V, Dr. (Mrs.) R. SUDARMANI"A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic", International Journal of Engineering Trends and Technology (IJETT), V22(1),27-30 April 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In low power design and high speed applications, a high resolution all digital duty cycle corrector (HR-ADDCC) is proposed. It is used to correct the duty cycle error and to achieve an exact 50% output duty cycle. A reversible multiplexer logic is used to obtain a glitch free circuit, which is more feasible compared to conventional logic gates. In addition, a reversible multiplexer based DCC (Duty Cycle Corrector) is proposed to achieve an exact 50% output duty cycle with low power area and high resolution duty cycle correction. It is suitable for wide operating frequency range in nanometer CMOS technology process.
.F. Mu and C. Svensson, “Pulsewidth control loop in high-speed CMOS clock buffers,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 134–141, Feb. 2000.
 P.-H. Yang and J.-S. Wang, “Low-voltage pulsewidth control loops for SOC applications,” IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1348–1351, Oct. 2002.
 S.-R. Han and S.-I. Liu, “A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle,” IEEE J. Solid-State Circuits,vol. 39, no. 3, pp. 463–468, Oct. 2004.
 K.-H. Cheng, C.-W. Su, and K.-F. Chang, “A high linearity, fast- locking pulsewidth control loop with digitally programmable duty cycle correction for wide range operation,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 399–413, Feb. 2008.
 Y.-J. Wang, S.-K. Kao, and S.-I. Liu, “All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles,” IEEE J. Solid- State Circuits, vol. 41, no. 6, pp. 1262–1274, Jun. 2006.
Duty Cycle Corrector (DCC), Delay Locked Loop (DLL), All-Digital Duty Cycle Corrector (ADDCC),Digitally Controlled Delay Line (DCDL).