Performance Enhancement of VLSI Circuits using CNTFETs
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2015 by IJETT Journal|
|Year of Publication : 2015|
|Authors : Siddiqui Sohail Ahmed H, Swapnali Makdey, Deepak Bhoir
|DOI : 10.14445/22315381/IJETT-V23P201|
Siddiqui Sohail Ahmed H, Swapnali Makdey, Deepak Bhoir "Performance Enhancement of VLSI Circuits using CNTFETs", International Journal of Engineering Trends and Technology (IJETT), V23(1),1-6 May 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In the world of integrated circuits, CMOS has lost it’s credential during scaling beyond 32nm. The main drawbacks of using CMOS transistors are high power consumption and high leakage current. Scaling causes severe Short Channel Effects (SCE) which are difficult to suppress. As technology is scaled down, the importance of leakage current and power analysis for VLSI design is increasing since short-channel effects cause an exponential increase in the leakage current and power dissipation. CNT-FET technologies mitigate these limitations by providing a stronger control over a thin silicon body. Enormous progress has been made to scale transistors to even smaller dimensions to obtain switching transistors that are fast and reduce the overall power consumption. However although the device characteristics are improved the problem of high active leakage still remain a problem. CNT-FET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect and the similarity of the fabrication steps to the existing standard CMOS technology. CNT-FET device has a higher controllability, resulting relatively high on/ off ratio. CNT-FET devices can be used to increase the performance by reducing the leakage current and power dissipation. The research work has, characteristics of CNT-FET, inverter &basic gates like NAND Gate, and are modelled in HSPICE software using CMOS structures and CNT-FET structure are analysed and their performances like power consumption and speed are compared. The values for Sub- Threshold slope of CNT-FET and MOSFETs are calculated.
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