Performance Enhancement of VLSI Circuits using CNTFETs

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2015 by IJETT Journal
Volume-23 Number-1
Year of Publication : 2015
Authors : Siddiqui Sohail Ahmed H, Swapnali Makdey, Deepak Bhoir
DOI :  10.14445/22315381/IJETT-V23P201


Siddiqui Sohail Ahmed H, Swapnali Makdey, Deepak Bhoir "Performance Enhancement of VLSI Circuits using CNTFETs", International Journal of Engineering Trends and Technology (IJETT), V23(1),1-6 May 2015. ISSN:2231-5381. published by seventh sense research group

In the world of integrated circuits, CMOS has lost it’s credential during scaling beyond 32nm. The main drawbacks of using CMOS transistors are high power consumption and high leakage current. Scaling causes severe Short Channel Effects (SCE) which are difficult to suppress. As technology is scaled down, the importance of leakage current and power analysis for VLSI design is increasing since short-channel effects cause an exponential increase in the leakage current and power dissipation. CNT-FET technologies mitigate these limitations by providing a stronger control over a thin silicon body. Enormous progress has been made to scale transistors to even smaller dimensions to obtain switching transistors that are fast and reduce the overall power consumption. However although the device characteristics are improved the problem of high active leakage still remain a problem. CNT-FET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect and the similarity of the fabrication steps to the existing standard CMOS technology. CNT-FET device has a higher controllability, resulting relatively high on/ off ratio. CNT-FET devices can be used to increase the performance by reducing the leakage current and power dissipation. The research work has, characteristics of CNT-FET, inverter &basic gates like NAND Gate, and are modelled in HSPICE software using CMOS structures and CNT-FET structure are analysed and their performances like power consumption and speed are compared. The values for Sub- Threshold slope of CNT-FET and MOSFETs are calculated.


[1] International Technology Roadmap for Semiconductors (ITRS) reports,
[2] Hong Li, Chuan Xu, Navin Srivastava, and Kaustav Banerjee, ?Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects, IEEE Trans. Electron Devices, vol. 56, no. 9, Sep, 2009.
[3] Ali Javey, Jing Guo, Qian Wang, Mark Lundstrom, and Hongjie Dai, ?Ballistic carbon nanotube field-effect transistor,? Nature, vol. 424, pp. 654-657, 2003.
[4] J. Guo, A. Javey, H. Dai, and M. Lundstrom, ?Performance analysis and design optimization of near ballistic carbon nanotube FETs,? IEDM Tech. Digest, pp. 703-706, 2004.
[5] R. Saito, G. Dresselhaus, and M. S. Dresselhaus, Physical Properties of Carbon Nanotubes. London: Imperial College Press, 1998.
[6] S. Das, S. Bhattacharya and D. Das, ?Modeling of carbon nanotube based device and interconnect using VERILOG-AMS?, Proc. Int. Conf. on Advances in Recent Technologies in Communication and Computing, pp. 51-55, Sep. 2011
[7] S. Das, S. Bhattacharya, D. Das, ?Performance Evaluation of CNTFET-based Logic Gates using Verilog-AMS?, Proc. National Conference on Electronics, Communication and Signal Processing, pp. 85-88, Sep. 2011.
[8] Busi, R., Swapna, P., Babu, K., Srinivasa, R., "Carbon Nanotubes Field Effect Transistors: A Review", International Journal of Electronics & Communication Technology, Vol.2, SP-1, Dec.2011, pp. 204-208.
[9] Andrew, D., Ervin, ?. "Effects of Differing Carbon Nanotube Fieldeffect Transistor Architectures",Army Research Laboratory, July 2009.
[10] Chen, Zhihong; Farmer, Damon; Xu, Sheng; Gordon, Roy; Avouris, Phaedon; Appenzeller, Joerg (2008). "Externally Assembled Gate-All- Around Carbon Nanotube Field-Effect Transistor". IEEE Electron Device Letters 29(2)183.
[11] Farmer, DB; Gordon, RG (2006). "Atomic layer deposition on suspended single-walled carbon nanotubes via gas-phase noncovalent functionalization". Nano letters6 (4): 699–703.
[12] Javey, Ali; Guo, Jing; Wang, Qian; Lundstrom, Mark; Dai, Hongjie (2003)."Ballistic carbon nanotube field-effect transistors". Nature 424 (6949): 654-7.
[13] S.Rasmita et al, "Simulation of Carbon Nanotube Field Effect Transistors," International Journal of Electronic Engineering Research, 117–125 Vol.1, No.2 (2009)
[14] Jing Guo; Datta, S.; Lundstrom, M.; Brink, M.; McEuen, P.; Javey, A.; Hongjie Dai; Hyoungsub Kim; McIntyre, P. (2002). "Digest.
International Electron Devices Meeting". p. 711 [15] Stanford University CNTFET Model.
[16] Digital Design Textbook by M.Morris Mano-Applied Electronics Engineering
[17] Modern Digital Electronics Textbook by Jain. Tata McGraw-Hill Education, Jun 1, 2003

Short channel effects, CNTFET.