Low Power Layout Design of Priority Encoder Using 65nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2015 by IJETT Journal
Volume-23 Number-9
Year of Publication : 2015
Authors : Amritesh Ojha, Rajesh Mehra
DOI :  10.14445/22315381/IJETT-V23P285


Amritesh Ojha, Rajesh Mehra"Low Power Layout Design of Priority Encoder Using 65nm Technology", International Journal of Engineering Trends and Technology (IJETT), V23(9),450-453 May 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

this paper provides comparative performance analysis of power and area of 4 bit priority encoder using 65nm technology. Two priority encoder approaches are presented, one with semi custom and the other with full custom. The main objective is to compare semi custom and full custom designed layout on the basis of two parameters which is power and area. Both the semi custom circuit simulation and full custom has been done by manually layout created. Creation of layout in both types of method is done at 65nm CMOS technology. The simulation results show that priority encoder using full custom design has improved power efficiency by 0.86 ?W and effective area by 12.40 ?m2.


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Priority Encoder, Low power, CMOS, 65nm.