Various Reduction Techniques for Parallel FIR Digital Filter Using Parallel Architecture
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2015 by IJETT Journal|
|Year of Publication : 2015|
|Authors : Kalyani R. Jambhulkar
|DOI : 10.14445/22315381/IJETT-V25P202|
Kalyani R. Jambhulkar" Various Reduction Techniques for Parallel FIR Digital Filter Using Parallel Architecture", International Journal of Engineering Trends and Technology (IJETT), V25(1),4-8 July 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
The FIR filter is a most widely used tools in digital signal processing and image processing applications. The aim is to design efficient Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure with the constraint that the filter tap must be a multiple of 2. In our work we have briefly discussed for L = 4 parallel implementation. The parallel FIR filter structure based on proposed FFA technique has been implemented based on carry save and ripple carry adder for further optimization. The reduction in silicon area complexity is achieved by eliminating the bulky multiplier with an adder namely ripple carry and carry save adder. Overall the new parallel FIR structures can lead to significant hardware savings for symmetric convolutions from existing FFA parallel FIR filter especially when the length of the filter is large.
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Digital signal processing (DSP) , Fast Finite Impulse Response (FIR) Algorithm (FFA) , Parallel FIR filter; FFA structure.