Comparator Design Analysis using Efficient Low Power Full Adder
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2015 by IJETT Journal|
|Year of Publication : 2015|
|Authors : Meena Aggarwal, Rajesh Mehra
|DOI : 10.14445/22315381/IJETT-V26P210|
Meena Aggarwal, Rajesh Mehra"Comparator Design Analysis using Efficient Low Power Full Adder", International Journal of Engineering Trends and Technology (IJETT), V26(1),50-54 August 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In today’s electronic industry, low power has emerged as principle theme. This reduction in power consumption and also in form of area, it makes the devices more reliable and efficient. So, CMOS technology has been developed which become best known for low power consumption and miniaturization in chip sizes. In a large-scale digital systems design, Comparator is a eminent to be the useful unit of digital systems and signal processors. In this paper , 32-bit comparator has been designed.. The above said designs are prepared by combining two different design approaches: Gate Diffusion Input (GDI) and PTL. These two techniques are hybridized in a way such that it takes the advantage of both the approaches in order to obtain the good quality performance of the circuit. The performance of this proposed 32-bit comparator by hybridizing the two design styles has been compared in terms of transistor count and power and also shows the effect of voltage variations on the power consumed by the circuit. The transistor level schematic are designed and simulated for its behavior using DSCH-3.1.The layout of simulated circuits are created using Verilog based netlist file which is then simulated in Microwind 3.1 to analyze the performance of comparators at 180 nm CMOS technology. The results shows that with the decrease in voltage, the power consumption also decreases but low voltage level results in increase delay.
 Suman Deb and S. Chaudhary, “High-Speed Comparator
Architectures for Fast Binary Comparison”, IEEE
International Conference on Emerging Applications of
Information Technology, pp. 454-457, 2012.
 Anjuli and Satyajit Anand, “2-Bit Magnitude Comparator design using different logic styles,” International Journal of Engineering Science Invention, Vol. 2, No. 1, pp.13-24, 2013.
 Anjali Sharma, Richa Singh, Rajesh Mehra, Member, IEEE, “Low Power TG Full Adder Design Using CMOS Nano Technology,” IEEE International Conference on Parallel, Distributed and Grid Computing, pp. 210-213.
 Vijay Kumar Sharma, Manisha Pattanaik, “VLSI Scaling methods and Low Power CMOS Buffer Circuit”, International Journal of Semiconductors, Vol. 34, No. 9, pp. 1-8, 2013.
 Dinesh Sharma and Rajesh Mehra, “Low power Delay Optimized Buffer Design using 70nm CMOS Technology,” International Journal of Computer Applications, Vol.22, No. 3, pp.13-18, 2011.
 P. Saini and R. Mehra, “A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits,” International Journal of Advanced Computer Science and Application, Vol.3, No.10, pp.161-168, 2012.
 Vandana Choudhary and Rajesh Mehra, “2-bit Comparator using Different Logic Style of Full Adder,” International Journal of Soft Computing and Engineering, Vol. 3, No.2, pp.277-279, 2013.
 Manoj Kumar, Sandeep K. Arya1, and Sujata Pandey, “ Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate”, International Journal of VLSI design & Communication Systems, Vol. 2, No. 4, pp. 47-59, 2011.
 Meena Aggarwal, Rajesh Mehra, “ Hybridized Power Efficient 32-bit Comparator using Less Transistor count”, International Journal of Advanced Research in Electronics and Communication Engineering, Vol. 4, No. 7, pp. 2012- 2018, 2015.
 Subodh Wairya, Himanshu Pandey, Rajendra Kumar Nagaria, Sudarshan Tiwari, “Ultra Low Voltage High Speed 1-bit CMOS Adder,” International Conference on Power Control And Embedded System, Vol.3, No.2, pp. 221-242, 2010.
 Morgenshtein, A., Fish A., Wagner, I.A., “Gate- diffusion input (GDI): A Power Efficient Method for Digital Combinational circuits,” IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 10 , No. 5 , pp. 566 - 581 , 2002.
 Chiou-Kou Tung, Yu-Cherng Hung, Shao-Hui Shieh, Guo- Shing Huang, “A Low -Power High-speed Hybrid CMOS Full Adder For Embedded System,” IEEE Transaction on Design and Diagnostics of Electronic Circuits and Systems, Vol.13, No.6, pp.1- 4, 2007.
 Po-Ming Lee, Chia-Hao Hsu, Yun-Hsiun Hung, “ Novel 10-T full adders realized by GDI structure,” Components, Circuits, Devices & Systems, Engineered Materials, Dielectrics & Plasmas, pp. 115 - 118 , 2007.
 A. Morgenshtein, A. Fish., A. Wagner, “Gate- Diffusion Input (GDI)-A novel power efficient method for digital circuits: A Design Methodology,” IEEE International Conference, pp. 39 – 43, 2001.
 Shahid Jaman, Nahian Chawdhury, Aasim Ullah, Muhammad Foyazur Raham, “ A New High Speed-Low Power 12 Transistor Full Adder Design With GDI Technique,” International Journal of Science & Engineering Research, Vol.3, No.7, 2012.
 Microwind and DSCH version 3.1, User’s Manual, Copyright 1997-2007, Microwind INSA France.
 N.Weste and D.Harris, CMOS VLSI Design: A Circuits and System Perspective, 3rd ed. Reading, MA, USA: Addison- Wesley May 2004.
ALU, Full Adder , Comparators, CMOS style, Digital Arithmetic, Full, GDI technique, Hybrid, PTL logic, Power Efficient.