Fused Add Then Multiply Implementation using Modified Booth Encoder
International Journal of Engineering Trends and Technology (IJETT) | |
|
© 2015 by IJETT Journal | ||
Volume-30 Number-2 |
||
Year of Publication : 2015 | ||
Authors : Chowtapalli Dayakar, P.Ranjith Kumar |
Citation
Chowtapalli Dayakar, P.Ranjith Kumar"Fused Add Then Multiply Implementation using Modified Booth Encoder", International Journal of Engineering Trends and Technology (IJETT), V30(2),50-54 December 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
Booth recoding is widely used to reduce the number of partial products in multipliers .Different recordings exist resulting in different gate level implementations and performance. In this work the XOR-based implementation gives lowest area and delay numbers in most technologies due to the small selector size and the well-balanced signal paths. An implementation of a radix-4 butterfly has been developed. The number of stages has been reduced. This reduction comes from the fact that, to achieve a throughput comparable to that of radix- 2. Therefore, the implementation of the radix-4 butterfly is suitable for high speed applications, since the hardware cost, the power consumption and the latency are reduced. To reduce the number of calculation steps for the partial products, MBA algorithm has been applied mostly where Wallace tree has taken the role of increasing the speed to add the partial product.
References
1. Y.-H. Seo and D.-W. Kim, ?A new VLSI architecture of parallel multiplier–accumulator based on Radix-2 modified Booth algorithm, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 201–208, Feb. 2010.
2. A. Peymandoust and G. de Micheli, ?Using symbolic algebra in algorithmic level DSP synthesis, in Proc. Design Automation Conf., Las Vegas, NV, 2001, pp. 277– 282.
3. W.-C. Yeh and C.-W. Jen, ?High-speed and low-power split-radix FFT, IEEE Trans. Signal Process., vol. 51, no. 3, pp. 864–874, Mar. 2003.
4. C. N. Lyu and D. W. Matula, ?Redundant binary Booth recoding, in Proc. 12th Symp. Comput. Arithmetic, 1995, pp. 50–57.
5. J. D. Bruguera and T. Lang, ?Implementation of the FFT butterfly with redundant arithmetic, IEEE Trans. Circuits Syst. Il, Analog Digit. Signal Process., vol. 43, no. 10, pp. 717–723, Oct. 1996.
6. W.-C. Yeh, ?Arithmetic Module Design and its Application to FFT, Ph.D. dissertation, Dept. Electron. Eng., National Chiao-Tung University, Chiao-Tung, 2001.
7. R. Zimmermann and D. Q. Tran, ?Optimized synthesis of sum-of-products, in Proc. Asilomar Conf. Signals, Syst. Comput., Pacific Grove, Washington, DC, 2003, pp. 867– 872.
8. B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. Oxford: Oxford Univ. Press, 2000. 9. O. L. Macsorley, ?High-speed arithmetic in binary computers, Proc. IRE, vol. 49, no. 1, pp. 67–91, Jan. 1961.
10. N. H. E. Weste and D. M. Harris, ?Datapath subsystems, in CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed. Readington: Addison-Wesley, 2010, ch. 11.
11. S. Xydis, I. Triantafyllou, G. Economakos, and K. Pekmestzi, ?Flexible datapath synthesis through arithmetically optimized operation chaining, in Proc. NASA/ESA Conf. Adaptive Hardware Syst., 2009, pp. 407– 414.
Keywords
Booth Encoder, Multiply, Add, Fused.