Cryptanalysis of AES using FPGA Implementation
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Mrs. Priyanka Holambe, Prof. Ms. Harshali D. Zodpe
|DOI : 10.14445/22315381/IJETT-V31P211|
Mrs. Priyanka Holambe, Prof. Ms. Harshali D. Zodpe"Cryptanalysis of AES using FPGA Implementation", International Journal of Engineering Trends and Technology (IJETT), V31(2),54-58 January 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In an age of technological advancements, security and privacy plays an important role in day to day communication. Cryptanalysis of modern cryptography algorithm involves massive and parallel computations. In absence of the mathematical breakthroughs to a cryptanalytical problem, a promising way to tackle these computations is to build special purpose hardware which will provide better costperformance ratio. In this paper, the cryptanalysis of AES algorithm using brute force attack is used as a proof of concept. The basic concept is to create multiple instances of the design which can be instantiated simultaneously so that the solution space is exposed at a faster rate. For implementation of AES, Spartan-6 (XC6LX9) device is used. FPGA implementation of the AES requiring 1918 slices on a Xilinx Spartan3 (XC3S50) device, while achieving throughput of 1114.624 Mbps. Time required for cryptanalysis of AES is reduced from seconds to miliseconds as 3 multiple instances of design are instantiated parallel. The low-cost implementation and moderate throughput makes it practically suitable for low resource security applications.
 Junfeng Chu , Mohammed Benaissa, “LOW AREA MEMORY-FREE FPGA IMPLEMENTA TION OF THE AES ALGO RITHM”, 978-1-4673-2256-0/12/$31.00 c 2012 IEEE, PP.623-626.
 Alan Kaminsky, Michael Kurdziel, Stanislaw Radziszowski, “An Overview of Cryptanalysis Research for the Advanced Encryption Standard”, 2010 Military Communications Conference - Unclassified Program - Cyber Security and Network Management 978-1-4244- 8179-8/10/$26.00 ©2010 IEEE
 William Stallings, “Cryptography and Network Security Principles and Practices”, Pearson Education, ISBN 81- 7758-774-9,2007.
 T. Good and M. Benaissa, “AES on FPGA from the Fastest to the Smallest,” LectureNotesinComputerScience,vol.3659,pp.427- 440, Sep. 2005.
 Federal Information Processing Standards Publication 197, “Advanced Encryption Standard (AES)”November26, 2001.
 P. Chodowiec, K. Gaj, Very Compact FPGA Implementation of the AES Algorithm, Cryptographic Hardware and Embedded Systems (CHES 2003), LNCS Vol. 2779, pp. 319 – 333, Spri nger - Verlag, October 2003.
 G. Rouvroy, F. X. Standaert, J. J. Quisquater, J. D. Legat, Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications, Procedings of the international conference on Information Technology: Coding and Computing 2004 (ITCC 2004), pp. 583 – 587, Vol. 2, April 2004.
 N. Pramstaller, S. Mangard, S. Dominikus, and J. Wolkerstorfer. Efficient AES implementations on ASICs and FPGAs. In Proc. 4th Conf. on the Advanced Encryption Standard (AES 2004), pp. 98 – 112, Bonn, Germany, May 10– 12, 2005.
 “Virtex-5 FPGA Data Sheet DS100 (v5.0)”, February6, 2009.
 Y. S. Jeon, Y. J. Kim, and D. H. Lee, “A Compact Memory-Free Architecture for the Aes Algorithm Using Resource Sharing Methods,” Journal of Circuits, Systems, and Computers, vol. 19, no. 5, p. 1109, 2010.
AES, FPGA, VHDL, Cryptanalysis, Brute-Force Attack, Cipher Key.