Cryptanalysis of AES using FPGA Implementation

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-31 Number-2
Year of Publication : 2016
Authors : Mrs. Priyanka Holambe, Prof. Ms. Harshali D. Zodpe
DOI :  10.14445/22315381/IJETT-V31P211


Mrs. Priyanka Holambe, Prof. Ms. Harshali D. Zodpe"Cryptanalysis of AES using FPGA Implementation", International Journal of Engineering Trends and Technology (IJETT), V31(2),54-58 January 2016. ISSN:2231-5381. published by seventh sense research group

In an age of technological advancements, security and privacy plays an important role in day to day communication. Cryptanalysis of modern cryptography algorithm involves massive and parallel computations. In absence of the mathematical breakthroughs to a cryptanalytical problem, a promising way to tackle these computations is to build special purpose hardware which will provide better costperformance ratio. In this paper, the cryptanalysis of AES algorithm using brute force attack is used as a proof of concept. The basic concept is to create multiple instances of the design which can be instantiated simultaneously so that the solution space is exposed at a faster rate. For implementation of AES, Spartan-6 (XC6LX9) device is used. FPGA implementation of the AES requiring 1918 slices on a Xilinx Spartan3 (XC3S50) device, while achieving throughput of 1114.624 Mbps. Time required for cryptanalysis of AES is reduced from seconds to miliseconds as 3 multiple instances of design are instantiated parallel. The low-cost implementation and moderate throughput makes it practically suitable for low resource security applications.[1]


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AES, FPGA, VHDL, Cryptanalysis, Brute-Force Attack, Cipher Key.