CMOS Design and Performance Analysis of Ring Oscillator for Different Stages
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Saikee Chauhan, Rajesh Mehra
|DOI : 10.14445/22315381/IJETT-V32P248|
Saikee Chauhan, Rajesh Mehra"CMOS Design and Performance Analysis of Ring Oscillator for Different Stages", International Journal of Engineering Trends and Technology (IJETT), V32(5),234-237 February 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
A ring oscillator is a circuit which consists of an odd number of inverter stages, where the output of each stage of the ring oscillator is given to the input of next stage and output of final stage is then fed to its input. Also, no external input is given to the device, only a reset pulse is provided at once and it drives the circuit. In this paper, the CMOS design and analysis of the ring oscillator have been performed for 5- stage, 7- stage and 9- stage using cadence virtuoso tool in 45nm technology. At the output of every stage of ring oscillator, a capacitor of 500aF and at the load, a capacitor of 5fF is used for different stages. The power consumption is reduced by 79% for 5-stage ring oscillator as compared to 9-stage ring oscillator.
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Ring oscillators, CMOS, System on Chip, frequency, power consumption, delay.