Area & Speed Efficient CIC Interpolator for Wireless Communination Application
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Hansa Rani Gupta, Rajesh Mehra
|DOI : 10.14445/22315381/IJETT-V34P248|
Hansa Rani Gupta, Rajesh Mehra "Area & Speed Efficient CIC Interpolator for Wireless Communination Application", International Journal of Engineering Trends and Technology (IJETT), V34(5),235-239 April 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
The aim of this paper to design and present a CIC Interpolator for SDR based wireless communication system. SDR system can provide a feasible solution which will be able to perform different function at different time on same hardware. Other requirements are high speed, improved area and low power consumption. The designing & implementation of Cascaded Integrator Comb Interpolator Filter with embedded look up tables increase speed as well as decrease the resources on FPGA’s target devices. The purposed CIC filter executes SRC efficiently using only adders & subtracts building it smart for SDR system. It will greatly enhance system performance and also cost which can be accomplished by reducing the immediate storage element and increase the reliability of the system. The CIC interpolator has been designed with MATLAB2013a, simulated with ISE Simulator, synthesis is done with XST, and implement on Spartan-3E XC3s500e-4fg320 target device. The planned design can be operated at an estimated frequency of 276.060 MHz by using very less resources available on FPGAs to offer useful solution for communication systems.
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CIC Filter, NGN, LUTs, 5G, SRC, SDR, FPGA.