Design & Analysis of Full Subtractor using 10T at 45nm Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Kamal Jeet Singh, Rajesh Mehra
|DOI : 10.14445/22315381/IJETT-V35P290|
Kamal Jeet Singh, Rajesh Mehra"Design & Analysis of Full Subtractor using 10T at 45nm Technology", International Journal of Engineering Trends and Technology (IJETT), V35(9),449-452 May 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In this paper, a 1-bit full subtractor is designed. In VLSI, a digital circuit can be design with different techniques and most popular techniques are conventional CMOS technique, GDI technique and MTCMOS technique. We prefer a circuit which have minimum number of transistor with good performance, less power consumption, less propagation delay and fast switching. In this paper, a full subtractoris designed using XOR gate and GDI technique. The technology node used is 45nm. Transient analysis for XOR gate and GDI technique based full subtractor is performed. In analysis, we found that the full subtractor designed with XOR gate uses less number of transistor and consume less power than GDI technique based full subtractor.Full subtractor using XOR gate uses 10T where GDI based uses 14T. Power consumption and time delay is improved by 36.04% and 36.13% respectively when compared with GDI based full subtractor.
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Full subtractor; GDI Technique; MTCMOS; XOR gate.