Design of Operational Amplifier in 45nm Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Aman Kaushik, Rajesh Mehra
|DOI : 10.14445/22315381/IJETT-V36P224|
Aman Kaushik, Rajesh Mehra"Design of Operational Amplifier in 45nm Technology", International Journal of Engineering Trends and Technology (IJETT), V36(3),125-129 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
This paper presents the designing and performance analysis of Operational Transconductance Amplifier using the 45nm Technology from mosis foundry. This transconductance design is having a biasing current of 5?A with supply voltage of ±1 V. The open loop gain obtained from this design is about 66.5 dB with UGB of 22 MHz is obtained from this design. This OTA design has a CMRR value of 74 dB and PSRR of 70 dB with Power dissipation of 68 ?W and Slew Rate 5 V/?sec. Simulation is done using UMC 45nm technology file.
1. Amalan Nag, K. L. Baishnab F. A. Talukdar, Member, IEEE “ Low Power, High Precision and Reduced Size CMOS Comparator for High Speed Design” 5th International Conference on Industrial and Information System, 2010 India.
2. Samanch Babayan-Mashhadi and Reza Lotfi, “ Analysis & Design of a Low Voltage Low-Power Double-Tail Comparator” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.22, No. 2, pp. 343-352, 2014.
3. Tanvi Sood, Rajesh Mehra, “ Design a Low Power Half- Subtractor Using .90?m CMOS Technology” IOSR Journal of VLSI and Signal Processing, Vol. 2, Issue 3, pp. 51-56, 2013.
4. V Choudhary, R Mehra “ 2-Bit Comparator Using Different Logic Style of Full Adder ”, International Journal of Soft Computing and Engineering, Volume 3, pp. 277-279, 2013.
5. Salch Abdel- Hafeez, “ Scalablr digital CMOS Comparator using a parallel prefix tree,” IEEE Transaction On Very Large Integration (VLSI) Systems, Vol.21, No. 11, pp. 1989-1997, 2013.
6. R. Nguyen and B. Murmann, ?The design of fast-settling twostage amplifiers using the open-loop damping factor as a design parameter, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 6, pp. 1244– 1254, 2010.
7. Prashant Upadhyay, Rajesh Mehra, “Low Power Design of 64-bits Memory by using 8-T Proposed SRAM Cell”, International Journal of Research and Reviews in Computer Science, Volume1, pp. 168-172, 2010.
8. P Saini, R Mehra, “ Leakage Power Reduction in CMOS VLSI Circuits ”, International Journal of Computer Application, Volume 55, pp. 42-88, 2012.
9. A Sharma, R Mehra “ Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI ”, International Journal of Computer Application, Volume 66, No. 4, pp. 975-8887, 2013
10. A Sharma, R Singh, R Mehra, “ Low Power TG full adder design using CMOS nano technology ”, Parallel Distributed and Grid Computing(PDGC), 2012 2nd IEEE International, pp. 210-213, 2012.
11. R Singh, R Mehra “ Power efficient design of multiplexer using adiabatic logic ”, International Journal of Advaces in Engineering & Technology, Volume 6, pp. 246-254, 2013.
12. Raghava Garipelly “ High Speed CMOS Comparator Design with 5mV ”, International Journal of Engineering Trends and Technology (IJETT), Volume 4, pp. 621-625, 2013.
13. Siddharth, Mehul Garg, Aditya Gahlaut “Comparative Study of CMOs Op-Amp in 45 nm and 180 nm Technology ”, Int. Journal of Engineering Research and Applications, Volume 4, pp. 64-67, 2014
Cadence, OperationTransconductance Amplifier (OTA), Slew Rate, Power Dissipation, Common mode rejection ratio.