Optimized Design and Simulation of Ring Counter using 45nm Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Sandeep Thakur, Rajesh Mehra
|DOI : 10.14445/22315381/IJETT-V36P235|
Sandeep Thakur, Rajesh Mehra"Optimized Design and Simulation of Ring Counter using 45nm Technology", International Journal of Engineering Trends and Technology (IJETT), V36(4),188-193 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In the era of technical world, sequential circuits are playing their vital role in the designing of digital system. Sequential circuit design with low power and high speed at smaller chip size has become the prime concern for researcher and day by day growth in VLSI technologies also sustain the flow for achieving the desired goals. A counter is a sequential circuit having various applications in the field of embedded system, pattern generations, signal synthesis, Digital to Analog conversion etc. In this paper, an optimized designing mechanism has been deployed to design a high speed, cost effective and low power 4-bit ring counter which can also be extended to higher order ring counter designs. In this work, performance of the proposed ring counter is enhanced by using a negative edge triggered master slave D flip flop which have 14 MOS transistors in its design as compare to conventional counter. The proposed paper has accomplished the design goals by reducing the 68.5% transistor count, 29.85% power consumption and got the 95% higher speed.
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Ring Counter; Master slave D flip flop; negative Edge trigged; VLSI power dissipation; Transistor count;CMOS gates.