Design and Performance Analysis of low Power Reversible Multipliers
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2016 by IJETT Journal|
|Year of Publication : 2016|
|Authors : Navsudeep Kaur, Mr. Amandeep Singh
|DOI : 10.14445/22315381/IJETT-V38P247|
Navsudeep Kaur, Mr. Amandeep Singh"Design and Performance Analysis of low Power Reversible Multipliers", International Journal of Engineering Trends and Technology (IJETT), V38(5),261-267 August 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Multipliers are one the greatest significant component of numerous schemes. So we continuously need to find a superior solution in case of multipliers. Our multipliers must always consume a smaller amount of power and cover less power. So over and done with our project and try to control which of the three algorithms works the best. In this dissertation obtainable circuit alternatives related with enterprise of a 4x4 nameless digital multiplier in RL and delineated the reversible multiplier application of minimal complexity. Unquestionably, the 4x4 multiplication circuit can be rummage-sale as a structure block for building RL multipliers of a superior bit-width. As upcoming research, we plan learning methods for complexity minimization in RL array multipliers having great bit-width as well as RL operations of signed multipliers.
 H. Bhagyalakshmi and M. Venkatesha, "An improved design of
a multiplier using reversible logic gates," International journal
of engineering science and technology, vol. 2, no. 8, pp. 3838-
 B. Sen, M. Dutta, D. K. Singh, D. Saran and B. K. Sikdar, "QCA multiplexer based design of reversible ALU," in Circuits and Systems (ICCAS), 2012 IEEE International Conference on, 2012.
 R. Saligram, S. S. Hegde, S. A. Kulkarni, H. Bhagyalakshmi and M. Venkatesha, "Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates," International Journal of Computer Applications, vol. 66, no. 19, 2013.
 H. Bhagyalakshmi and M. Venkatesha, "Design of a multifunction BVMF reversible logic gate and its applications," International Journal of Computer Applications, pp. 975-8887, 2011.
 A. K. Thakre, S. S. Chiwande and S. D. Chafale, "Design of low power multiplier using reversible logic gate," in Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on, 2014.
 M. A. Kumar, O. R. Rao, M. Dileep, C. P. K. Reddy and K. Mani, "Performance Evaluation of Different Multipliers in VLSI using VHDL," Performance Evaluation, vol. 5, no. 3, 2016.
 R. P. Feynman, "Quantum mechanical computers," Foundations of physics, vol. 16, no. 6, pp. 507-531, 1986.
 G. U. K. S. H. B. Sonali S. Kothule, "A Review on Vedic Multiplier using Reversible," International Journal of Innovative Research in Science,, vol. 5, no. 4, pp. 5838-5844, 2016.
 L. K. Grover, "A framework for fast quantum mechanical algorithms," in Proceedings of the thirtieth annual ACM symposium on Theory of computing, 1998.
 V. G. Moshnyaga, "Design of minimum complexity reversible multiplier," in TENCON 2015-2015 IEEE Region 10 Conference, 2015.
 Santosh Rani and Amandeep Singh Bhandari, “A Survey on Reversible Logic Gates”, International Journal of Computer Applications (0975 – 8887), pp. 1-3.
 Ashima Malhotra, Charanjit Singh, Amandeep Singh, “Efficient Design of Reversible Multiplexers with Low Quantum Cost”, Int. Journal of Engineering Research and Applications, Vol. 4, Issue 7( Version 4), July 2014, pp.20-23.
 Sukhjeet Kaur and Amandeep Singh Bhandari, “Design and Performance Analysis of Encoders using Reversible logic gates”, International Conference on Advancements in Engineering and Technology (ICAET 2015).
 Singh, Manjinder Pal, Birinderjit Singh, and Amandeep Singh Bhandari. "Performance Analysis of Low Power Decoders Using Reversible Computing." International Journal of Research 2, no. 11 (2015): 253-260.
As upcoming research, we plan learning methods for complexity minimization in RL array multipliers having great bit-width as well as RL operations of signed multipliers.