Architectural Level Power Optimization Techniques for Multipliers
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2012 by IJETT Journal|
|Year of Publication : 2012|
|Authors : V.Alekhya , B.Srinivas|
V.Alekhya , B.Srinivas. "Architectural Level Power Optimization Techniques for Multipliers". International Journal of Engineering Trends and Technology (IJETT). V3(5):574-578 Sep-Oct 2012. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In this work, a new topology wa s proposed to optimize the power dissipation of Multipliers. Low power digital Multiplier Design based on bypassing technique mainly used to reduce the switching power dissipation. While this technique offers great dynamic power savings mainly in array mul tipliers, due to their regular interconnection scheme, it misses the reduced area and high speed advantages of tree multipliers. Therefore, mixed style architecture, using a traditional tree based part, combined with a bypass, array based part, is proposed . Prototyping of all these multiplier Architectures has been carried out on Spartan3E FPGA. By Evaluating the performance of these Multiplier architectures using Xilinx ISE tool suite , it has been found that while the bypass technique offers the minimum d ynamic power consumption, the mixed architecture offers a delay*power product improvement , compared to all other architectures.
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