Architectural Level Power Optimization Techniques for Multipliers

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2012 by IJETT Journal
Volume-3 Issue-5                       
Year of Publication : 2012
Authors :  V.Alekhya , B.Srinivas


V.Alekhya , B.Srinivas. "Architectural Level Power Optimization Techniques for Multipliers". International Journal of Engineering Trends and Technology (IJETT). V3(5):574-578 Sep-Oct 2012. ISSN:2231-5381. published by seventh sense research group


In this work, a new topology wa s proposed to optimize the power dissipation of Multipliers. Low power digital Multiplier Design based on bypassing technique mainly used to reduce the switching power dissipation. While this technique offers great dynamic power savings mainly in array mul tipliers, due to their regular interconnection scheme, it misses the reduced area and high speed advantages of tree multipliers. Therefore, mixed style architecture, using a traditional tree based part, combined with a bypass, array based part, is proposed . Prototyping of all these multiplier Architectures has been carried out on Spartan3E FPGA. By Evaluating the performance of these Multiplier architectures using Xilinx ISE tool suite , it has been found that while the bypass technique offers the minimum d ynamic power consumption, the mixed architecture offers a delay*power product improvement , compared to all other architectures.


1) Dimitris Bekiaris, George Economakos and Kiamal Pekmestzi, "A Mixed Style Multiplier Architecture for Low Dynamic and Leakage Power Dissipation," in International Symposium on VLSI Design Automation and Test (VLSI - DAT). IEEE, 20 10, pp. 258 - 261
2) M. Karlsson, “A generalized carry - save adder array for digital signal processing,” in 4th Nordic Signal Processing Symposium. IEEE, 2000, pp. 287 – 290.
3) P. Meier, R. A. Rutenbar, and L. R. Carley, “Exploring multiplier architecture and layout for low power,” in Custom Integrated Circuits Conference. IEEE, 1996, pp. 513 – 516.
4) N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective - Third Edition. Addison - Wesley, 2004.
5) C. C. Wang and G. N. Sung, “Low - power multiplier design using a bypassing technique,” Journal of Signal Processing Systems, 2008.
6) S. Kim, S. Hong, M. Papaefthymiou, and W. E. Stark, “Low power parallel multiplier design for dsp applications through coefficient optimization,” in 12th Annual International ASIC/SO C Conference. IEEE, 1999, pp. 286 – 290.
7) G. Economakos and K. Anagnostopoulos, “Bit level architectural exploration technique for the design of low power multipliers,” in International Symposium on Circuits and Systems. IEEE, 2006.