Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2013 by IJETT Journal|
|Year of Publication : 2013|
|Authors : B. Dilli Kumar , M. Bharathi|
B. Dilli Kumar , M. Bharathi. "Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic". International Journal of Engineering Trends and Technology (IJETT). V4(1):32-40 Jan 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Low power has emerge d as a principle theme in today electronic industry. Energy efficiency is one of the most important features of modern electronic systems designed for high speed and portable applications. The power consumption of the electronic devices can be reduced by adopting different design styles. Adiabatic logic style is said to be an attractive solution for such low power electronic applications. This paper presents an energy efficient technique for digital circuits that uses adiabatic logic. The proposed technique has less power dissipation when compared to the conventional CMOS design style. This paper evaluates the full adder in different adiaba tic logic styles and their results were compared with the conventional CMOS design. The simulation results indicate that t he proposed technique is advantageous in many of the low power digital applications.
 Atul Kumar Maurya and Ganesh Kumar, “ Adiabatic Logic: Energy Efficient Technique for VLSI Applications ”, International Conference on Computer& Communication Technology (ICCCT) - 2011.
 Vojin G. Oklobd"zija, Dragan Maksimovi` c, "Pass - Transistor Adiabatic Logic Using Single Power - Clock Supply ", IEEE Transactions on Circuits a nd Systems, Vol. 44, No. 10, October 1997.
 A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low power CMOS digital design,’’ IEEE J. Solid - State Circ. , vol. 27, no. 4, pp.473 - 484, Apr. 1992.
 T. Indermauer and M. Horowitz, “Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power Design,” Technical Digest IEEE Sym. Low Power Electroni cs, San Diego, pp. 102 - 103, Oct. 2002 .
 Arsalan, M. Shams, M., “Charge - recovery power clock generators for adiabatic logic circuits”, 18th International Conference on VLSI Design, pp. 171 - 174, 3 - 7 January 2005.
 Dragan Maksimovic et al, “Clocked CMOS adiabatic Logic with Integrated Single Phase Power Clock Supply”, IEEE Transactions on VLSI Systems, vol 8, No 4, pp 460 - 463, August 2000.
 W.C. Athas, L. Svensson, J.G. Koller et ,N.Tzartzanis and E.Y.Chou: “Low - power Digital Systems Bared on Adi abatic - switching Principles”. IEEE Transactions on VLSI Systems. Vol. 2, No. 4, pp. 398 - 407 December. 1994.
[8 ] Satyam Mandavilli, Prashanth Paramahans “ An Efficient Adiabatic Circuit Design Approach for” International Journal of Recent Trends in Engine ering, Vol 2, No. 1, November 2009 Low Power Applications .
 A. Vetuli, S. Di Pascoli, and L.M. Reyneri, “Positive feedback inadiabatic logic,” Electron.Lett.,vol.32, pp.1867 - 1869, Sept. 1996 .
[10 ] N. Anuar, Y. Takahashi, T. Sekine, “Two phase clocked adiabatic static CMOS logic,” proc. IEEE SOCC 2009, pp. 83 - 86, Oct. 2009.
 N. Anuar, Y. Takahashi, T. Sekine, “Two - Phase clocked adiabatic static CMOS logic and its logic family” Journal of semiconductor technology and science, vol 10, no. 1, Mar. 20 10.
Adiabatic, Charge recovery, low power, energy efficient, digital circuits, sinusoidal power clock .