Analysis of Read-stability and Write-ability in FinFET SRAM cells
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Ashish Kumar Sharma, Nikhil Saxena
|DOI : 10.14445/22315381/IJETT-V44P210|
Ashish Kumar Sharma, Nikhil Saxena "Analysis of Read-stability and Write-ability in FinFET SRAM cells", International Journal of Engineering Trends and Technology (IJETT), V44(1),53-56 February 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
SRAM cells are designed exclusively to guarantee that the data of the cell is not altered during read access and the cell can quickly change its state during write operation. These conflicting needs for read and write operations are contented by some specific conditions to provide stable read and write operations, SRAM cell read stability and write ability is most important concerns in nanometer scale technologies, due to the progressive increase in intra die variability and Vdd scaling. In conventional six transistors (6T) SRAM cell, read stability is very low due to the voltage division between the access and driver transistors during read operation. Analysis has been done with the factors responsible to improve the read stability and write ability of 6T SRAM cell structures. SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation.
 T.Skotnicki , M. Sellier, A. Farcy, and F. Boeuf, “An evaluation of the CMOS technology roadmap from the point of view of variability, interconnects, and power dissipation.” IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1433–1440, Jun. 2008.
 B. Cheng et al., “The impact of random doping effects on CMOS SRAM cell,” in Proc. ESSCIRC, Sep. 2004, pp. 219–222.
 Li Ding and P. Mazumder. Dynamic noise margin: definitions and model. In VLSI Design, 2004. Proceedings. 17th International Conference on, pages 1001 – 1006, 2004.
 S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi and V. De, “Parameter Variations and Impact on Circuits and Microarchitecture”, Proc. DAC, 2003, pp. 338-342.
 B Calhoun and A Chandrakasan. Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE Journal of Solid State Circuits, 41:1673, 2006.
 M. Khellah, Y. Ye, N. S. Kim, D. Somasekhar, G. Pandya, A. Farhang, K. Zhang, C. Webb and V. De, “Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vdd 45nm CMOS designs,” Symp. on VLSI Circuits, pp. 9-10, June 2006.
 D. A. Antoniadis, I. Aberg, C. N. Chléirigh, O. M. Nayfeh,A. Khakifirooz, and J. L. Hoyt, “Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations,” IBM J. Research Development, vol.050, no.4, pp. 363–376, Jul. 2006.
 K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep sub micrometer CMOS circuits,” Proceeding of IEEE, vol.91, no.2, pp.305–327, Feb. 2003.
Read stability, write ability, Cell Ratio, Pull up transistor, SRAM cell, Static Noise Margin (SNM)