Performance Evaluation in Adiabatic Logic Circuits for Low Power VLSI Design
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Tabassum Ara, Amrita Khera
|DOI : 10.14445/22315381/IJETT-V45P250|
Tabassum Ara, Amrita Khera "Performance Evaluation in Adiabatic Logic Circuits for Low Power VLSI Design", International Journal of Engineering Trends and Technology (IJETT), V45(5),241-245 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
As the in semiconductor industries progress by following Moore’s law faithfully from last five decades, and integrating more transistors along with functional circuits on a single chip periodically with every coming process technology. However, this progress help in rapid run towards tiny, circuit design high speed and economical VLSI (Very Large Scale of Integration) circuits has added to excessive power dissipation of numerous circuits used today. In this research paper we have study the different topologies of adiabatic logic such as ECRL, 2N-2N2P and PFAL. The main objective of this paper is to calculate the power consumption, Delay and PDP of the existing adiabatic logic families, and thus compare for the effectiveness in terms of lower power dissipation. All simulations were performed by using HSPICE Simulator at 65nm technology having 10MHz frequency at supply voltage is 1V, for proper validation and verification of the results W/L ratio of all the circuit is kept constant.
 M.L. Keote, P.T. Karule, "Design and Implementation of
Energy Efficient Adiabatic ECRL and Basic Gates," International
Conference on Soft Computing Techniques and Implementations-
(ICSCTI), Oct 8-10, 2015.
 J.S. Denker “A review of adiabatic computing,” In: IEEE Symposium on Low Power Electronics, San Diego, 1994. 94–97.
 B. H. Calhoun, S. Khann and R. Mann, “Sub-threshold circuit design with shrinking CMOS devices,” IEEE International Symposium on Circuits and Systems, Taipei, pp. 2541–2544, 2009.
 S. Hemantha, A. Dhawan and K. Haranath, “Multi-threshold CMOS design for low power digital circuits,” 2008 IEEE Region 10 Conference on TENCON, pp. 1-5, Hyderabad, 2008.
 Y. Moon and D.K. Jeong, “An efficient charge recovery logic circuit,” IEEE Journal of Solid-State Circuits, Vol. 31, 1996, pp. 514-522 as accessed on October, 2014.
 A. Kramer, J.S. Denker et al., “2nd order adiabatic computing with 2N-2N and 2N-2N2P logic circuits,” Proc. Intern. Symp. Low Power Design, 1995, pp. 191-196 as accessed on September, 2014.
 A. Vetuli, S. Di Pascoli and L. M. Reyneri, “ Positive feedback in adiabatic logic,” Electronics Letters, Vol. 32, No. 20, Sep. 1996, pp. 1867 as accessed on July,2014.
 A. Blotti , S. Di Pascoli and R. Saletti, “Simple model for positive feedback adiabatic logic power consumption estimation,” Electronics Letters. Vol. 36, No. 2, Jan, 2000, pp. 116-118 as accessed on March, 2014.
 K. Roy and Y. Ye,” Low Power Circuit Design using Adiabatic Switching Principle”, ECE Technical Reports, Purdue University, Indiana, as accessed on April, 2013.
 A. Chaudhary, M. Saha, M. Bhowmik et. al., "Implementation Of Circuit In Different Adiabatic Logic," IEEE Sponsored 2nd International Conference On Electronics And Communication System,ICECS, 2015.
 N. Liao, K. Liao et. al., “Low power adiabatic logic based on FinFETs”, Science China Information Sciences, Vol. 57, pp. 022402:1–022402:13, February 2014.
 S.K. Kelly and J.L. Wyatt, “A Power Efficient Neural Tissue Stimulator with Energy Recovery,” IEEE Transactions on Biomedical Circuits and Systems, Vol.5, No. 1, pp. 20-29, Feb. 2011.
 D. Shinghal, A. Saxena and A. Noor, “Adiabatic Logic Circuits: A retrospective,” MIT International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, pp. 108–114, August 2013.
 S.P. Kushawaha and T.N. Sasamal, “Modified Positive Feedback Adiabatic Logic for Ultra Low Power VLSI,” IEEE International Conference on Computer, Communication and Control (IC4-2015).
 R. Singh, A. Sharma and R. Singh, "Power Efficient Design of Multiplexer based Compressor using Adiabatic Logic," International Journal of Computer Applications (0975 – 8887), Vol. 81, No. 10, November 2013.
C-CMOS, ECRL, 2N-2N2P, Power, Delay.