Implementation of Power Optimized 2 Bit Polar Decoder Architectures
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Badugu Neelima, A.Vijaya Lakshmi
Badugu Neelima, A.Vijaya Lakshmi "Image forensic, Copy-move forgery,SURF.", International Journal of Engineering Trends and Technology (IJETT), V45(7),288-294 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
There are so many different error correcting codes are existed for the design environment correction. Among those polar codes, as the first provable capacity-achieving codes over binary-input discrete memoryless channel (B-DMC). However, for polar codes, the long latency is a bottleneck for designing. In this paper, a mitigation technique is proposed and adopted to avoid latency drawbacks in polar codes. Maintaining less prone to errors in circuits is very important to avoid data corruption in the system. This paper presents a new built-in 2-D Hamming product code (2–D HPC) scheme to provide reliable operation of polar codes in hostile operating environment applications such as space. Error correction method which in used in this paper is 2-D HPC which can enhances the reliability. By the Simulation waveforms the functionality of the 2-D HPC method which is used for polar codes should be understand with the clear sense. The HDL code is developed with VERILOG language and the synthesis and simulation is done by XILINX ISE EDA Tool.
 “Virtex-5 FPGA User Guide,” Xilinx Corp., San Jose, CA [Online]. Available: http://www.xilinx.com,
 A. Leseaet al., “The Rosetta experiment: Atmospheric soft error rate testing in different technology FPGAs, IEEE Trans. Device Mater. Rel., vol. 5, no. 3,
 E. Fuller et al., “Radiation testing update, SEU mitigation, and availability analysis of the Virtex FPGA for space reconfigurable computing,” inProc. MAPLD.
 R. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies, ”IEEE Trans. Device Mater. Rel.., vol. 5, no. 3, pp. 305–316.
 A. Lesea et al., “The Rosetta experiment: Atmosperic soft error rate testing in differing technology FPGAs,” IEEE Trans. Device Mater.
 E. Fuller et al., “Radiation testing update, SEU mitigation, and availability analysis of the Virtex FPGA for space reconfigurable computing,” in Proc. MAPLD, 2000.
 J. F. Ziegler, “Terrestrial cosmic ray intensities,” IBM J. Res. Develop., vol. 42, no. 1, pp. 117–139, 1998.
 E. Normand, “Single event effects in avionics,” IEEE Trans. Nucl. Sci. vol. 43, no. 2, pp. 461–474, Apr. 1996.
 R. Baumann, “Radiation-induced soft errors in advanced semiconductor technologies,” IEEE Trans. Device Mater. Rel.., vol. 5, no. 3, pp. 305–316, Sep. 2005.
 H. Asadi et al., “Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs,” (VLSI) Syst., vol. 16, no. 12,
 C. Carmichael et al., “SEU mitigation techniques for Virtex FPGAs in space applications,” in Proc. MAPLD, 1999.
 K. Chapman et al., “SEU strategies for Virtex-5 devices,” Xilinx Application
 M. Garvie et al., “Scrubbing away transients and jiggling around the permanent: Long survival of FPGA systems through evolutionary selfrepair,”
Soft errors, polar codes, Xilinx, Verilog.