A Efficient Technique For Low-Power High Speed Adder Circuit Design in DSM Technology
Citation
Anuj Dev, Sandip Nimade "A Efficient Technique For Low-Power High Speed Adder Circuit Design in DSM Technology", International Journal of Engineering Trends and Technology (IJETT), V47(1),25-31 May 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
The necessity for low-power design is
also important in high performance digital systems,
such as microprocessors and digital signal
processors because of high integration density and
the high clock frequency. In this paper we presented
a new 13T full adder design based on hybrid –
CMOS logic design style. The new design is
compared with some existing designs for power
consumption, delay, PDP at various frequencies
such as 10 MHz, 200 MHz and 1 GHz. the
simulations are carried out on Cadence Virtuoso at
65nm CMOS technology and the simulation results
are analyzed to verify the superiority of the proposed
design over the existing designs. Maximum saving of
power delay product is at low frequency by proposed
circuit is 90.8% with respect to C-CMOS and
significant improvement is observed at other
frequencies also for proper validation and
verification of the results W/L ratio of all the circuit
is kept constant.
References
[1] U. Ko, P. Balsara, and W. Lee, “Low-power design
techniques for high-performance CMOS adders,” IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 2, pp. 327–333,
Jun. 1995.
[2] A. Shams, T. Darwish, and M. Bayoumi, “Performance
analysis of low power 1-bit CMOS full adder cells,” IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20–29,
Feb. 2002.
[3] M. Alioto and G. Palumbo, “Analysis and comparison on full
adder block in submicron technology,” IEEE Trans. Very Large
Scale (VLSI) Syst., vol. 10, no. 6, pp. 806–823, Dec. 2002.
[4] P. J. Song and G. De Micheli, “Circuit and architecture tradeoffs
for high-speed multiplication,” IEEE J. Solid-State Circuits,
vol. 26, no. 9, pp. 1184–1198, Sep. 1991.
[5] A. P. Chandrakasan and R. W. Brodersen, Low Power Digital
CMOS Design. Norwell, MA: Kluwer, 1995.
[6] Z. Wang, G. Jullien, and W. C. Miller, “A new design
technique for column compression multipliers,” IEEE Trans.
Comput., vol. 44, no. 8, pp. 962–970, Aug. 1995.
[7] R. Zimmermann and W. Fichtner, “Low-power logic styles:
CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits,
vol. 32, pp. 1079–90, July 1997.
[8] Vahid Foroutan, Mohammad Reza Taheri, Keivan Navi,
Arash Azizi Mazreah “ Design of two Low-Power full adder cells
using GDI structure and hybrid CMOS logic style”,Integration,
the VLSI Journal, Vol.47,no.1, pp 48-61 January 2014.
[9] R. Uma and P. Dhavachelvan, ”Modified Gate Diffusion
Input Technique: A New Technique for Enhancing Performance
in Full Adder Circuits”, Proc. Of ICCCS, vol. 6, pp. 74-81, 2012.
[10] Nabiallah Shiri Asmangerdi, Javad Forounchi, Kuresh
Ghanbari,“ A New 8- Transistors Floating Full-Adder Circuit”,
20th Iranian Conf. Electrical Engineering, (ICEE2012), May-
2012.
[11] M. Zhang, J. Gu, and C. H. Chang, “A novel hybrid pass
logic with static CMOS output drive full-adder cell,” in Proc.
IEEE Int. Symp. Circuits Syst., May 2003, pp. 317–320.
[12] S. Goel, Ashok Kumar and M. A. Bayoumi, “Design of
robust, energy efficient full adders for deep-submicrometer design
using Hybrid-CMOS logic style”, IEEE Trans. Very Large Scale
Intsgr. (VLSI) Syst., vol. 14, no. 12, Dec. 2006.
[13] A.Bazzazi and B. Eskafi, “Design and Implementation of
Full Adder Cell with the GDI Technique Based on 0.18?m
CMOS Technology”, proceedings of the International multiconference
of engineers and computer scientists, 2010.
[14] T. Kalavathidevi and C. Venkatesh, “Area Efficient Low
Power VLSI Architecture for A Viterbi Decoder Using Gate
Diffusion Input (GDI) Logic Style”, European Journal of
Scientific Research, vol.49, no.4, pp. 521-532, 2011.
[15] PrathyushaKonduri andMageshKannan.P , “ Low Power
RAM using Gate-Diffusion-Input Technique : A Comparison with
Static CMOS” , International Journal Of Advanced Engineering
Sciences and Technologies, vol. 5, no. 2, pp.195 - 200 , 2011.
[16] R.Uma and P. Dhavachelvan, “Modified Gate Diffusion
Input Technique: A New Technique for Enhancing Performance
in Full Adder Circuits”, 2nd International Conference on
Communication, Computing & Security, pp. 74-81 -2012.
[17] VahidForoutan, MohammadRezaTaheri, KeivanNavi, and
ArashAziziMazreah, “Design of two Low-Power full adder cells
using GDI structure and hybrid CMOS logic style”,
INTEGRATION, the VLSI journal, vol. 47, pp.48–61, 2014.
Keywords
Low power, GDI, SERF, Hybrid adder.