A Efficient Technique For Low-Power High Speed Adder Circuit Design in DSM Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Anuj Dev, Sandip Nimade
|DOI : 10.14445/22315381/IJETT-V47P203|
Anuj Dev, Sandip Nimade "A Efficient Technique For Low-Power High Speed Adder Circuit Design in DSM Technology", International Journal of Engineering Trends and Technology (IJETT), V47(1),25-31 May 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
The necessity for low-power design is also important in high performance digital systems, such as microprocessors and digital signal processors because of high integration density and the high clock frequency. In this paper we presented a new 13T full adder design based on hybrid – CMOS logic design style. The new design is compared with some existing designs for power consumption, delay, PDP at various frequencies such as 10 MHz, 200 MHz and 1 GHz. the simulations are carried out on Cadence Virtuoso at 65nm CMOS technology and the simulation results are analyzed to verify the superiority of the proposed design over the existing designs. Maximum saving of power delay product is at low frequency by proposed circuit is 90.8% with respect to C-CMOS and significant improvement is observed at other frequencies also for proper validation and verification of the results W/L ratio of all the circuit is kept constant.
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Low power, GDI, SERF, Hybrid adder.