Design and Comparison of Low Power High Performance Online Testable Combinational Circuits with Different Reversible Logic Gates
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Ranjusha K, Remya K P, Salmanul Faris
|DOI : 10.14445/22315381/IJETT-V47P222|
Ranjusha K, Remya K P, Salmanul Faris "Design and Comparison of Low Power High Performance Online Testable Combinational Circuits with Different Reversible Logic Gates", International Journal of Engineering Trends and Technology (IJETT), V47(3),132-138 May 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In current scenario, the reversible logic design attracting more interest due to its low power consumption. Reversible logic is very important in low-power VLSI design,quantum computing, nanotechnology and optical computing. In this paper, a new 4*4 reversible gate termed OTG (Online Testable Gate) and CTSG are proposed suitable for online testability in reversible logic circuits. OTG can also work singly as a reversible full adder with a bare minimum of two garbage outputs. OTG is shown better than the recently proposed R1 gate (introduced for providing online testability in reversible logic circuits), in terms of computation complexity. The proposed reversible gate is combined with the existing 4*4 Feynman gate to design online testable reversible adders such as ripple carry adder, carry skip adder and BCD adder and 4*1 Multiplexers and De Multiplexers. The important reversible gates used for reversible logic synthesis are Feynman Gate, Fredkin gate, toffoli gate, New Gate, DKG Gate and peres gate etc. The proposed system is the design of basic reversible gate and comparison of leakage power, dynamic power, total power. The testable reversible circuits proposed in this work are shown to be better than the recently proposed testable designs in terms of number of reversible gates, garbage outputs and unit delay.The reversible logic circuits are designed and implemented using VHDLcode. The synthesize and simulation results are obtained in Xilinx ISE version 10.1i and MODEL SIM 6.4a.
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Garbage outputs, Online Testable Gate(OTG), Power consumption, Reversible logic circuits, CTSG, Feynman Gate, Fredkin gate, Toffoli gate, DKG Gate, Peres Gate and Xilinx ISE version 10.1i and MODEL SIM 6.4a.