VLSI Implementation of Lifting Based 3-D DWT
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : M.Prethippa, N.Usha Bhanu
|DOI : 10.14445/22315381/IJETT-V47P231|
M.Prethippa, N.Usha Bhanu "VLSI Implementation of Lifting Based 3-D DWT", International Journal of Engineering Trends and Technology (IJETT), V47(4),187-192 May 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
This paper proposes an efficient architecture for lifting based 3-D DWT Lifting based for video/ image signal using parallel pipeline technique. The main objective of this paper is to minimize the critical path delay in computing the 9/7 lossy lifting steps with reduced clock cycles. The architecture consists of row, column and temporal processors and video frames are processed using separability and cyclic symmetry property. The novelty of this method is by using flipping structure for adders and replacing multipliers by shift and add operations. This benefits the proposed method for low latency, power consumption, and high throughput over many existing architectures. To validate this model, the architecture is being coded in Verilog HDL and implemented using Xilinx ISE 14.7xc7a100t-3-csg324 FPGA. The performance of this architecture of 3D lifting DWT processor achieves a speed of at least 373 MHZ with low power dissipation making it suitable for real time high speed video applications.
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Lifting DWT, Parallel processing,Cyclic symmetry Property, Critical path delay, Video processing, pipelining.