Dynamically Reconfigurable RISC Microprocessor design using MIPS Instruction Set
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Neethu K Krishnan, Bhavya Das D
|DOI : 10.14445/22315381/IJETT-V47P246|
Neethu K Krishnan, Bhavya Das D "Dynamically Reconfigurable RISC Microprocessor design using MIPS Instruction Set", International Journal of Engineering Trends and Technology (IJETT), V47(5),287-289 May 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Today’s world suggests multifunction in each products. This paper design a RISC processor using MIPS instruction set architecture which supports multifunctioning. Dynamic Reconfiguration refers to the ability of the Processor to update its internal Instruction Decode and Execute stage in order to support new functions, while the system is running. This project presents a principle on how performance can be improved in the context of microprocessor Units applications, using the MIPS instruction set.
 P.V.S.R.Bharadwaja, K. Ravi Teja, M.Naresh babu,
K.Neelima ( 2015,May 20-21) Advanced Low Power
RISC Processor Design using MIPS Instruction, IEEE
International Conference On Recent Trends In Electronics
and Communication systems.
 Gautham P, Parthasarathy R, Karthi Balasubramanian (2014) Low-Power Pipelined MIPS Processor Design .
 Mrs. Rupali S. Balpande. Mrs.Rashmi S. Keote. (2014,May) Design of FPGA based Instruction Fetch & Decode Module of 32-bit RISC (MIPS) Processor, 2011 International Conference on Communication Systems and Network Technologies
 Panjali S Kalgoankar,Prof.Shilpa.Kodgire Design of 32 bit MIPS RISC Processor based on SoC, International journal of latest trends in Engineering and technology(IJLTET)
 Zulkifli.M, Yudhanto, Y.P, Soetharyo NAdionoT Reduced Stall MIPS Architecture using Pre-Fetching Accelerator., 2009 International Conference on Electrical Engineering and Informatics5-7 August 2009, Selangor, Malaysia
 R.Uma,“Design and Performance Analysis of 8-bit RISC Processor using Xilinx Tool”2012 International Journal of Engineering Research and Applications (IJERA)
 Anand Nandakumar Shardul, “16-Bit RISC Processor Design for Convolution Application”, -2013 International Journal of Advancements in Research & Technology.
 Ciletti, Michael D. “Advanced Digital Design with the Verilog HDL.”Upper Saddle River, NJ: Pearson Education Inc. 2003
 Sagar Bhavsar , Akhil Rao , Abhishek Sen , Rohan Joshi ,” A 16-bit MIPS Based Instruction Set Architecture for RISC Processor” April 2013 International Journal of Scientific and Research Publications.
 V. B. Saambhavi and V. S. Kanchana Bhaaskarana,” 16-bit RISC microprocessor using dcpal circuits” International Journal of Advanced Engineering Technology
 .Dalal, A.Ganesh, Aishwarya.D “An 8 bit Power-Efficient MIPS Processor “ Advanced VLSI Design Sping 2014.
RISC, MIPS, dynamically reconfigurable.