An Area Efficient 3T XNOR cell based Low Power Full adder using 32nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2017 by IJETT Journal
Volume-49 Number-3
Year of Publication : 2017
Authors : Ramesh Jangir, Ramakant Vyas
DOI :  10.14445/22315381/IJETT-V49P222


Ramesh Jangir, Ramakant Vyas "An Area Efficient 3T XNOR cell based Low Power Full adder using 32nm Technology", International Journal of Engineering Trends and Technology (IJETT), V49(3),145-149 July 2017. ISSN:2231-5381. published by seventh sense research group

Full adder cells are the bricks of arithmetic & logical modules and these modules are bricks of the microprocessors and DSP. In the current age of technology advancement it is necessary to design different new concepts to reduce area of the cell as well as power consumption. In this paper CMOS gates have been used to develop the proposed XNOR bricks using 3 transistors and mux using 2 transistors. These bricks are designed to reduce the power consumption and the chip area occupied by it. The proposed design of full adder uses 8 CMOS transistors (3 PMOS + 5 NMOS). The reduction in CMOS transistors improves area and power performance. The proposed full adder cell have been designed using 32 nm CMOS technologies. The developed full adder cell with 3T XNOR bricks with have shown an improvement of 47% in power and 23.92% in area using DSCH3.5, Microwind 3.1tool at 32nm CMOS technology so as to implement adder cell efficiently for DSP applications.


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DSCH, full adder, transmission gate (TG), Mux, and XNOR.