An Area Efficient 3T XNOR cell based Low Power Full adder using 32nm Technology
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Ramesh Jangir, Ramakant Vyas
|DOI : 10.14445/22315381/IJETT-V49P222|
Ramesh Jangir, Ramakant Vyas "An Area Efficient 3T XNOR cell based Low Power Full adder using 32nm Technology", International Journal of Engineering Trends and Technology (IJETT), V49(3),145-149 July 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Full adder cells are the bricks of arithmetic & logical modules and these modules are bricks of the microprocessors and DSP. In the current age of technology advancement it is necessary to design different new concepts to reduce area of the cell as well as power consumption. In this paper CMOS gates have been used to develop the proposed XNOR bricks using 3 transistors and mux using 2 transistors. These bricks are designed to reduce the power consumption and the chip area occupied by it. The proposed design of full adder uses 8 CMOS transistors (3 PMOS + 5 NMOS). The reduction in CMOS transistors improves area and power performance. The proposed full adder cell have been designed using 32 nm CMOS technologies. The developed full adder cell with 3T XNOR bricks with have shown an improvement of 47% in power and 23.92% in area using DSCH3.5, Microwind 3.1tool at 32nm CMOS technology so as to implement adder cell efficiently for DSP applications.
 J. M. Wang, S. C. Fang, and W. S. Feng, “New efficient designs for XOR and XNOR functions on the transistor level,” IEEE J. Solid-State Circuits, vol. 29, no. 7, pp. 780–786, Jul. 1994.
 Y. Leblebici and S.M. Kang, CMOS Digital Digital Integrated Circuits, Singapore: Mc Graw Hill, India, 2nd edition, 1999.
 H. T. Bui, A. K. Al Sheraidah, and Y.Wang, “New 4-transistor XOR and XNOR designs,” in Proc. 2nd IEEE Asia Pacific Conf. ASIC, 2000, pp. 25–28.
 H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using XOR-XNOR gates,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, vol. 49, no. 1, pp. 25– 30, Jan. 2002.
 S. Goel, M. E. Elgamel, M. A. Bayouni, and Y. Hanafy, “Design methodologies for high- performance noise-tolerant XOR-XNOR circuits,” IEEE Trans. Circuits and Syst. I, vol. 53, no. 4, Apr. 2006.
 Shiv Shankar Mishra et.al. “New design methodologies for high speed low power XOR-XNOR circuits,” World Academy of Science, Engineering and Technology, vol.55, pp.200-206, 2009.
 Sohan Purohit and Martin Margala, “Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance” IEEE Transaction Very Large Scale Integration (VLSI) Systems, Vol. 20, no.7, pp.1327-1331, July 2012
 Anjali Sharma, Richa Singh and Rajesh Mehra, “Low Power TG Full Adder Design Using CMOS Nano Technology”, 2nd IEEE International Conference on Parallel, Distributed and Grid Computing, pp. 210-213, 2012
 Buddhi Prakash Sharma and Rajesh Mehra, “High Speed & Power Efficient Inverter using 90nm MTCMOS Technique,” International Journal of Scientific Research Engineering & Technology, pp. 21-25, August 2014.
 Shivani Singh, Buddhi Prakash Sharma, Sanjay Singhal, “An Area Efficient Low Power TG Full Adder Design using CMOS Nano Technology”, International Journal of Engineering Research & Technology (IJERT), ISSN: 2278-0181, Vol. 3 Issue 4, April – 2014, pp. 2197-2201.
 Partha Bhattacharyya, BijoyKundu,SovanGhosh, Vinay Kumar and AnupDandapat, “Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit”, IEEE Trans. Very Large Scale Intsgr. (VLSI) Syst., vol. 23, no. 10, October 2015.
 D.lakshmaiah, T.sai baba et. Al, “Design of Low Power CMOS Three Input XOR/XNOR”, International Journal of computer science and Electronics Engineering UK, Vol. 6, Issue 1, pp. 1-6, May 2016.
 Krati Katiyar and Praveen Kumar, “Low-Power High Speed 1-bit Full Adder Circuit Design in DSM Technology”, International Journal of Emerging Research in Management &Technology, Vol. 6, Issue 4, April 2017.
DSCH, full adder, transmission gate (TG), Mux, and XNOR.