Implementation of 128, 192 & 256 bits Advanced Encryption Standard on Reconfigurable Logic
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2017 by IJETT Journal|
|Year of Publication : 2017|
|Authors : Monika Gupta, Swapnil Mahto, Ambresh Patel
|DOI : 10.14445/22315381/IJETT-V50P251|
Monika Gupta, Swapnil Mahto, Ambresh Patel "Implementation of 128, 192 & 256 bits Advanced Encryption Standard on Reconfigurable Logic", International Journal of Engineering Trends and Technology (IJETT), V50(6),305-309 August 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Advanced encryption standard is adopted by NIST to replace data encryption standard, which was affected by several attacks. In this paper implementation of all three modes namely 128, 192 and 256 of advanced encryption standard is discussed for reconfigurable logic. All these modes are implemented using four design architectures namely: 2 stage sequential, 3 stage sequential , combinational and pipelined.
 Hammad I, El-Sankary K, El-Masry E, “High-speed AES encryptor with efficient merging techniques,” IEEE Embedded Systems Letters, 2010, pp.67-71.
 I ZHANG Y L, WANG X G, “Pipelined implementation of AES encryption based on FPGA,” 2010 IEEE International Conference on Information Theory and Information Security, Piscataway: IEEE, 2010, pp. 170-173.
 FAN C-P, HWANG J-K, “Implementations of high throughput sequential and fully pipelined AES processors on FPGA.” ISPACS 2007: Proceeding of 2007 International Symposium on International Signal Processing and Symposium and Communication Systems, Piscataway: IEEE, 2007, pp. 353-356.
 SKLAVOS N, KOUFOPAVLOU O, “Architectures and VLSI implementations of the AES-proposal Rijndael,” IEEE Transactions on Computers, 2002, 51(12), pp. 1454-1459.
 BORKAR A M, KSHIRSAGAR R V, VYAWAHARE M V, “FPGA implementation of AES algorithm,” The 3rd International Conference on Electronics Computer Technology, Piscataway: IEEE, 2011, 3, pp. 401-405.
 Joan Daemen,Vincent Rijmen.AES Proposal:Rijdael. The Rijndael Block Cipher.
 Vincent Rijmen, “Efficient implementation of the of the rijndael SBox,” 2000.
 FISCHER V, DRUTAROVSKY M, CHODOWIEC P, “InvMixColunm decomposition and multilevel resource sharing in AES implementations,” IEEE Transactions on Very Large Scale Integration Systems, 2005, 13(8), pp. 989-992.
 Chien M Ta, Chee Hong Yong, Wooi Gan Yeoh, “A 2.7mW, 0.064mm2linear-in-dB VGA with 60dB tuningrange, 100MHz bandwidth, and two DC offset cancellation loops,” IEEE International
 Workshop on Radio Frequency Integration Technology, Austria: Graz, 2005, pp. 74-77.
 J.Balamurugan, Dr.E.Logashanmugam “High Speed Low Cost Implementation of Advanced Encryption Standard on FPGA” ICCET 2014.
Advanced encryption standard, Sequential, combinational, pipelined, encryption, cryptography.